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1.发明授权公开(公告)号：US10778482B2
公开(公告)日：2020-09-15
申请号：US16515248
申请日：2019-07-18
Applicant: Texas Instruments Incorporated
Inventor： Nikolaus Klemmer , Amneh Mohammed Akour , Abhijit Anant Patki , Timothy Patrick Pauletti , Tarkesh Pande
Abstract: An integrated circuit includes a bit slicing circuit with a processing circuit. The processing circuit receives discrete frequency power estimates based on an S-FSK waveform received by an S-FSK receiver associated with the bit slicing circuit. The discrete frequency power estimates are representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. Each data frame including at least one word. Each word includes bit periods. The processing circuit receives SNR parameters that represent a dynamic SNR for the respective discrete frequency power estimates in relation to the series of data frames. The processing circuit selects a bit slicing technique from a set of available bit slicing techniques to generate data bit values for bit periods of the discrete frequency power estimates based on the SNR parameters. A method for performing bit slicing in an S-FSK receiver is also disclosed.
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2.发明申请公开(公告)号：US20200259687A1
公开(公告)日：2020-08-13
申请号：US16515248
申请日：2019-07-18
Applicant: Texas Instruments Incorporated
Inventor： Nikolaus Klemmer , Amneh Mohammed Akour , Abhijit Anant Patki , Timothy Patrick Pauletti , Tarkesh Pande
Abstract: An integrated circuit includes a bit slicing circuit with a processing circuit. The processing circuit receives discrete frequency power estimates based on an S-FSK waveform received by an S-FSK receiver associated with the bit slicing circuit. The discrete frequency power estimates are representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. Each data frame including at least one word. Each word includes bit periods. The processing circuit receives SNR parameters that represent a dynamic SNR for the respective discrete frequency power estimates in relation to the series of data frames. The processing circuit selects a bit slicing technique from a set of available bit slicing techniques to generate data bit values for bit periods of the discrete frequency power estimates based on the SNR parameters. A method for performing bit slicing in an S-FSK receiver is also disclosed.
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公开(公告)号：US10728068B2
公开(公告)日：2020-07-28
申请号：US15860988
申请日：2018-01-03
Applicant: Texas Instruments Incorporated
IPC: H04L27/22 , H03D3/00 , H03L7/081 , H04L27/227 , H03K19/21 , H03L7/087 , H03L7/113 , H04L7/033 , H04L7/00
Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase.
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4.发明授权公开(公告)号：US11265191B2
公开(公告)日：2022-03-01
申请号：US16944562
申请日：2020-07-31
Applicant: Texas Instruments Incorporated
Inventor： Nikolaus Klemmer , Amneh Mohammed Akour , Abhijit Anant Patki , Timothy Patrick Pauletti , Tarkesh Pande
Abstract: An integrated circuit includes a bit slicing circuit with a processing circuit. The processing circuit receives discrete frequency power estimates based on an S-FSK waveform received by an S-FSK receiver associated with the bit slicing circuit. The discrete frequency power estimates are representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. Each data frame including at least one word. Each word includes bit periods. The processing circuit receives SNR parameters that represent a dynamic SNR for the respective discrete frequency power estimates in relation to the series of data frames. The processing circuit selects a bit slicing technique from a set of available bit slicing techniques to generate data bit values for bit periods of the discrete frequency power estimates based on the SNR parameters. A method for performing bit slicing in an S-FSK receiver is also disclosed.
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5.发明授权公开(公告)号：US11196596B2
公开(公告)日：2021-12-07
申请号：US17018366
申请日：2020-09-11
Applicant: Texas Instruments Incorporated
Inventor： Nikolaus Klemmer , Amneh Mohammed Akour , Abhijit Anant Patki , Timothy Patrick Pauletti , Tarkesh Pande
Abstract: An integrated circuit includes a bit slicing circuit with a processing circuit. The processing circuit receives discrete frequency power estimates based on an S-FSK waveform received by an S-FSK receiver associated with the bit slicing circuit. The discrete frequency power estimates are representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. Each data frame including at least one word. Each word includes bit periods. The processing circuit receives SNR parameters that represent a dynamic SNR for the respective discrete frequency power estimates in relation to the series of data frames. The processing circuit selects a bit slicing technique from a set of available bit slicing techniques to generate data bit values for bit periods of the discrete frequency power estimates based on the SNR parameters. A method for performing bit slicing in an S-FSK receiver is also disclosed.
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Patent Agency Ranking
公开(公告)号：US20180006856A1
公开(公告)日：2018-01-04
申请号：US15200706
申请日：2016-07-01
Applicant: Texas Instruments Incorporated
CPC classification number: H04L27/22 , H03D3/00 , H03K19/21 , H03L7/081 , H03L7/087 , H03L7/113 , H04L7/0087 , H04L7/0331 , H04L27/2271
Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase; when the data signal is oscillating at the first phase, output a first logic value; and when the data signal is oscillating at the second phase, output a second logic value, the output of the fast phase change detection circuit being used to determine whether the first output signal or the second output signal will be utilized in the feedback loop of the low bandwidth phase lock loop.
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7.发明申请公开(公告)号：US20200313945A1
公开(公告)日：2020-10-01
申请号：US16900010
申请日：2020-06-12
Applicant: Texas Instruments Incorporated
Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase.
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公开(公告)号：US10763889B1
公开(公告)日：2020-09-01
申请号：US16661456
申请日：2019-10-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Uttam Kumar Agarwal , Anand Kannan , Ramamurthy Vishweshwara , Anand Subramanian , Pedro Ramon Gelabert , Diljith Mathal Thodi , Abhijit Anant Patki
Abstract: A circuit includes a programmable gain amplifier (PGA) having a PGA output. The circuit further includes a delta-sigma modulator having an input coupled to the PGA output. The circuit also includes a digital filter and a dynamic range enhancer (DRE) circuit. The digital filter is coupled to the delta-sigma modulator output. The DRE circuit is coupled to the delta-sigma modulator output and to the PGA. The DRE circuit is configured to monitor a signal level of the delta-sigma modulator output. Responsive to the signal level being less than a DRE threshold, the DRE circuit is configured to program the PGA for a gain level greater than unity gain and to cause the digital filter to implement an attenuation of a same magnitude as the gain level to be programmed into the PGA.
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公开(公告)号：US09893916B2
公开(公告)日：2018-02-13
申请号：US15200706
申请日：2016-07-01
Applicant: Texas Instruments Incorporated
CPC classification number: H04L27/22 , H03D3/00 , H03K19/21 , H03L7/081 , H03L7/087 , H03L7/113 , H04L7/0087 , H04L7/0331 , H04L27/2271
Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase; when the data signal is oscillating at the first phase, output a first logic value; and when the data signal is oscillating at the second phase, output a second logic value, the output of the fast phase change detection circuit being used to determine whether the first output signal or the second output signal will be utilized in the feedback loop of the low bandwidth phase lock loop.
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10.发明公开公开(公告)号：US20240295864A1
公开(公告)日：2024-09-05
申请号：US18216224
申请日：2023-06-29
Applicant: Texas Instruments Incorporated
Inventor： Lokesh Kumar Botcha , Abhijit Anant Patki
IPC: G05B19/18
CPC classification number: G05B19/188 , G05B2219/45031
Abstract: An example apparatus includes a register, a memory to store reconfiguration data associated with the register, and register control circuitry. The example register control circuitry is to determine whether the memory includes the reconfiguration data corresponding to a trigger event experienced by state machine circuitry. Additionally, the example register control circuitry is to, based on determining that the memory includes the reconfiguration data corresponding to the trigger event, reconfigure the register identified in the reconfiguration data with a value included in the reconfiguration data.
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