公开(公告)号：US20250037759A1

公开(公告)日：2025-01-30

申请号：US18360373

申请日：2023-07-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Robin Osa HOEL ,  Aniruddha PERIYAPATNA NAGENDRA ,  Prithvi Shankar YEYYADI ANANTHA ,  Shobhit SINGHAL

IPC: G11C11/413

Abstract: In an example, a system includes an SRAM configured to store a plurality of access control rules, where each rule is stored in a separate row. The SRAM is configured to store a plurality of context entries, where each context entry is stored in a separate row. The system includes a controller configured to receive a request for an access control rule for a memory location from a first context. The controller is configured to search one or more access control rules for the first context, where access control rules for the first context are stored in a binary tree format. The controller is configured to, responsive to finding the access control rule for the memory location, return the access control rule to the first context. The controller is configured to, responsive to not finding the access control rule, return a null notification to the first context.

公开(公告)号：US20210203786A1

公开(公告)日：2021-07-01

申请号：US16730776

申请日：2019-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shobhit SINGHAL ,  Vikas LAKHANPAL ,  Preetam TADEPARTHY

IPC: H04M11/00 ,  G06F9/38 ,  A61N1/372 ,  G01R19/12

Abstract: Aspects of the disclosure provide for a circuit, in some examples, including a storage element, a co-processor, and a telemetry sequencer coupled to the storage element and the co-processor. The telemetry sequencer is configured to implement a digital state machine to receive configuration information indicating a type of telemetry data for generation, retrieve operations and operands, where the operations and the operands define a sequential series of actions for execution to generate the telemetry data, drive the co-processor with the operations and the operands by passing some of the operations and some of the operands to the co-processor for processing by the co-processor, receive, from the co-processor, and store an intermediate output of the series of actions as the telemetry data in a first format, and receive, from the co-processor, and store a final output of the series of actions as the telemetry data in a second format.

公开(公告)号：US20240134548A1

公开(公告)日：2024-04-25

申请号：US18389989

申请日：2023-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shobhit SINGHAL ,  Ruchi SHANKAR ,  Sverre BRUBAEK ,  Praveen KUMAR N

IPC: G06F3/06

CPC classification number: G06F3/0635 ,  G06F3/0619 ,  G06F3/0673

Abstract: A memory system includes a main memory, an auxiliary memory, a redundancy circuit, an extension control terminal, and a multiplexer. The main memory has a line width, and includes a write data input. The auxiliary memory has the same line width as the main memory, and includes a write data input. The redundancy circuit includes and input and an output. The input is coupled to the write data input of the main memory. The multiplexer includes a first input, a second input, a control input, and an output. The first input is coupled to the write data input of the main memory. The second input is coupled to the output of the redundancy circuit. The control input is coupled to the extension control terminal. The output of the multiplexer is coupled to the write data input of the auxiliary memory.

公开(公告)号：US20230244396A1

公开(公告)日：2023-08-03

申请号：US17590884

申请日：2022-02-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shobhit SINGHAL ,  Ruchi SHANKAR ,  Sverre BRUBAEK ,  Praveen KUMAR N

IPC: G06F3/06

CPC classification number: G06F3/0635 ,  G06F3/0619 ,  G06F3/0673

Abstract: A memory system includes a main memory, an auxiliary memory, a redundancy circuit, an extension control terminal, and a multiplexer. The main memory has a line width, and includes a write data input. The auxiliary memory has the same line width as the main memory, and includes a write data input. The redundancy circuit includes and input and an output. The input is coupled to the write data input of the main memory. The multiplexer includes a first input, a second input, a control input, and an output. The first input is coupled to the write data input of the main memory. The second input is coupled to the output of the redundancy circuit. The control input is coupled to the extension control terminal. The output of the multiplexer is coupled to the write data input of the auxiliary memory.

公开(公告)号：US20210119435A1

公开(公告)日：2021-04-22

申请号：US16658311

申请日：2019-10-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mayank JAIN ,  Preetam TADEPARTHY ,  Rohit NARULA ,  Shobhit SINGHAL

IPC: H02H3/20 ,  H02H1/00 ,  G06F1/30

Abstract: An over/under voltage protection circuit includes a voltage input terminal, a digital-to analog converter, a comparator, and a control circuit. The comparator includes a first input coupled to an output of the digital-to-analog converter, and a second input coupled to the voltage input terminal. The control circuit includes an output coupled to an input of the digital-to-analog converter, and an input coupled to an output of the comparator. The control circuit is configured to set the digital-to-analog converter to generate an overvoltage fault threshold responsive to the output of the comparator indicating that voltage of a signal at the voltage input terminal exceeds a threshold currently generated by the digital-to-analog converter.