公开(公告)号：US20250030436A1

公开(公告)日：2025-01-23

申请号：US18399223

申请日：2023-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anand SUBRAMANIAN ,  Tanmay HALDER ,  Deepa NAIR J S ,  Sreeja CHAKINGAL

IPC: H03M3/00

Abstract: In a described example, a circuit includes a digital-to-analog converter (DAC) unit element switch circuit including first and second sign switch inputs, first and second select switch inputs, and first, second and third DAC outputs. Synchronizer logic includes a selection input and first and second synchronization outputs, in which the first synchronization output is coupled to the first select switch input and the second synchronization output is coupled to the second select switch input. Selection logic includes a data input, a sign control output and a selection control output, in which the sign control output is coupled to the first and second sign switch inputs, and the selection control output is coupled to the selection input.

公开(公告)号：US20250030431A1

公开(公告)日：2025-01-23

申请号：US18496436

申请日：2023-10-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Tanmay HALDER ,  Anand SUBRAMANIAN ,  Anand KANNAN

IPC: H03M1/08

Abstract: In some examples, a circuit includes a first integrator having an input and an output. The circuit also includes a switching architecture having first and second terminals, the first terminal of the switching architecture coupled to the output of the first integrator. The circuit also includes a second integrator having an input and an output, the input of the second integrator coupled to the second terminal of the switching architecture. The circuit also includes a quantizer having an input and an output, the input of the quantizer coupled to the output of the second integrator. The circuit also includes a digital processing circuit having an input and an output, the input of the digital processing circuit coupled to the output of the quantizer.

公开(公告)号：US20250030391A1

公开(公告)日：2025-01-23

申请号：US18590280

申请日：2024-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Laxmi Vivek TRIPURARI ,  Anand SUBRAMANIAN ,  Tanmay HALDER ,  Anand KANNAN ,  Priyanshu PANDEY

IPC: H03G3/34 ,  H03F3/183 ,  H04R3/00

Abstract: In some examples, a circuit includes a first transistor having a control terminal and first and second terminals. The circuit also includes a first capacitor having first and second terminals, the first terminal of the first capacitor coupled to the control terminal of the first transistor and the second terminal of the first capacitor coupled to the second terminal of the first transistor. The circuit also includes a first switch having first and second terminals, the second terminal of the first switch coupled to the control terminal of the first transistor. The circuit also includes a second capacitor having first and second terminals, the first terminal of the second capacitor coupled to the first terminal of the first transistor and the second terminal of the second capacitor coupled to the first terminal of the first switch.

公开(公告)号：US20210044267A1

公开(公告)日：2021-02-11

申请号：US16789540

申请日：2020-02-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anand SUBRAMANIAN ,  Tanmay HALDER ,  Anand KANNAN

IPC: H03F3/45 ,  H03G3/30 ,  H03M1/12

Abstract: A circuit includes an analog-to-digital converter (ADC). The circuit also includes an analog front end (AFE) having an AFE input and an AFE output. The AFE output is coupled the ADC's input. The AFE includes a programmable gain amplifier (PGA) having a first PGA input and a second PGA input. The PGA includes a first operational amplifier (OP AMP) with first and second OPAMP inputs. The AFE also including a programmable resistance circuit having a first programmable resistance circuit input and first and second programmable resistance circuit outputs. The first programmable resistance circuit input is coupled to the first and second PGA inputs. The programmable resistance circuit includes a resistor network having first and second balance resistances. The first balance resistance is coupled to the first and second OP AMP inputs, and the second balance resistance is coupled to the first and second OP AMP inputs.