MONOLITHIC REFERENCE ARCHITECTURE WITH BURST MODE SUPPORT
    1.
    发明申请
    MONOLITHIC REFERENCE ARCHITECTURE WITH BURST MODE SUPPORT 审中-公开
    具有BURST模式支持的单片参考架构

    公开(公告)号:US20170068265A1

    公开(公告)日:2017-03-09

    申请号:US15259368

    申请日:2016-09-08

    CPC classification number: G05F1/575

    Abstract: A reference circuit may include a bandgap reference stage, a filter stage, and a buffer stage. The reference stage may be configured to generate a reference voltage or current. The filter stage may be coupled to the reference stage and may be configured to receive the reference voltage or current, filter noise from the reference voltage or current, receive a buffer output voltage or current, and filter noise from the buffer output voltage or current. The buffer stage may be coupled to the filter stage and may be configured to isolate the reference stage and the filter stage from a loading effect of a load circuit and generate a reference signal based on the reference voltage or current to drive the load circuit.

    Abstract translation: 参考电路可以包括带隙基准级,滤波级和缓冲级。 参考级可以被配置为产生参考电压或电流。 滤波器级可以耦合到参考级,并且可以被配置为从参考电压或电流接收参考电压或电流,滤波器噪声,接收缓冲器输出电压或电流,以及从缓冲器输出电压或电流滤除噪声。 缓冲级可以耦合到滤波器级,并且可以被配置为将参考级和滤波级与负载电路的负载效应隔离,并且基于参考电压或电流产生参考信号以驱动负载电路。

    CIRCUIT WITH DYNAMIC CURRENT SENSE CALIBRATION

    公开(公告)号:US20240230815A1

    公开(公告)日:2024-07-11

    申请号:US18478384

    申请日:2023-09-29

    CPC classification number: G01R35/005 G01R19/25 H04R29/001

    Abstract: A circuit includes: a driver circuit; a sense resistor; a test circuit; a current sense circuit; a calibration controller; and a switch controller. The current sense circuit is configured to: obtain first sense signals responsive to a test voltage applied to the sense resistor by the test circuit, the test voltage being a direct-circuit voltage; and obtain second sense signals responsive a supply voltage applied to the sense resistor by the driver circuit, the supply voltage including a common-mode voltage. The calibration controller is configured to calibrate the current sense circuit responsive to the first sense signals and the second sense signals. The switch controller is configured to update switch control signals provided to the driver circuit responsive to current sense signals obtained by the calibrated current sense circuit.

    PIECEWISE CORRECTION OF ERRORS OVER TEMPERATURE WITHOUT USING ON-CHIP TEMPERATURE SENSOR/COMPARATORS

    公开(公告)号:US20170083038A1

    公开(公告)日:2017-03-23

    申请号:US14949390

    申请日:2015-11-23

    CPC classification number: G05F3/245

    Abstract: A temperature dependent correction circuit includes a first supply source, a second supply source, a rectifying circuit, and a reference. The first supply source is configured to supply a first signal that varies with temperature along a first constant or continuously variable slope. The second supply source is configured to supply a second signal that varies with temperature along a second constant or continuously variable slope. The rectifying circuit is configured to receive the first and second signal, rectify the first signal to produce a first rectified signal, and add the first rectified signal to the second signal to produce a correction signal. The reference is configured to receive the correction signal.

    ADC ARCHITECTURE INCORPORATING CONTINUOUS-TIME QUANTIZER

    公开(公告)号:US20250030431A1

    公开(公告)日:2025-01-23

    申请号:US18496436

    申请日:2023-10-27

    Abstract: In some examples, a circuit includes a first integrator having an input and an output. The circuit also includes a switching architecture having first and second terminals, the first terminal of the switching architecture coupled to the output of the first integrator. The circuit also includes a second integrator having an input and an output, the input of the second integrator coupled to the second terminal of the switching architecture. The circuit also includes a quantizer having an input and an output, the input of the quantizer coupled to the output of the second integrator. The circuit also includes a digital processing circuit having an input and an output, the input of the digital processing circuit coupled to the output of the quantizer.

    MULTIPLEXER CHARGE INJECTION REDUCTION
    7.
    发明申请
    MULTIPLEXER CHARGE INJECTION REDUCTION 审中-公开
    多路复用器充电注入减少

    公开(公告)号:US20170040990A1

    公开(公告)日:2017-02-09

    申请号:US15231350

    申请日:2016-08-08

    Abstract: A multiplexer comprises: a first switch; a second switch; a dummy component coupled to the first switch and the second switch and configured to: reduce a first charge injection of the first switch, and reduce a second charge injection of the second switch; and an output coupled to the first switch, the second switch, and the dummy component. A method comprises: providing an output from either a first switch or a second switch; coupling, by a dummy component, to the first switch and the second switch; using a BBM action; and reducing, by the dummy component, a first charge injection of the first switch or a second charge injection of the second switch.

    Abstract translation: 多路复用器包括:第一开关; 第二个开关 耦合到所述第一开关和所述第二开关的虚拟部件,其被配置为:减少所述第一开关的第一电荷注入,并且减少所述第二开关的第二电荷注入; 以及耦合到第一开关,第二开关和虚拟部件的输出。 一种方法包括:提供来自第一开关或第二开关的输出; 通过虚拟部件耦合到第一开关和第二开关; 使用BBM动作; 以及通过所述虚拟部件减小所述第一开关的第一电荷注入或所述第二开关的第二电荷注入。

    POP-CLICK-NOISE (PCN) REDUCTION IN AUDIO DRIVER

    公开(公告)号:US20250030391A1

    公开(公告)日:2025-01-23

    申请号:US18590280

    申请日:2024-02-28

    Abstract: In some examples, a circuit includes a first transistor having a control terminal and first and second terminals. The circuit also includes a first capacitor having first and second terminals, the first terminal of the first capacitor coupled to the control terminal of the first transistor and the second terminal of the first capacitor coupled to the second terminal of the first transistor. The circuit also includes a first switch having first and second terminals, the second terminal of the first switch coupled to the control terminal of the first transistor. The circuit also includes a second capacitor having first and second terminals, the first terminal of the second capacitor coupled to the first terminal of the first transistor and the second terminal of the second capacitor coupled to the first terminal of the first switch.

    PROGRAMMABLE GAIN AMPLIFIER WITH PROGRAMMABLE RESISTANCE

    公开(公告)号:US20210044267A1

    公开(公告)日:2021-02-11

    申请号:US16789540

    申请日:2020-02-13

    Abstract: A circuit includes an analog-to-digital converter (ADC). The circuit also includes an analog front end (AFE) having an AFE input and an AFE output. The AFE output is coupled the ADC's input. The AFE includes a programmable gain amplifier (PGA) having a first PGA input and a second PGA input. The PGA includes a first operational amplifier (OP AMP) with first and second OPAMP inputs. The AFE also including a programmable resistance circuit having a first programmable resistance circuit input and first and second programmable resistance circuit outputs. The first programmable resistance circuit input is coupled to the first and second PGA inputs. The programmable resistance circuit includes a resistor network having first and second balance resistances. The first balance resistance is coupled to the first and second OP AMP inputs, and the second balance resistance is coupled to the first and second OP AMP inputs.

    MULTIPLEXER CHARGE INJECTION REDUCTION
    10.
    发明申请

    公开(公告)号:US20200259492A1

    公开(公告)日:2020-08-13

    申请号:US16860736

    申请日:2020-04-28

    Abstract: A multiplexer comprises: a first switch; a second switch; a dummy component coupled to the first switch and the second switch and configured to: reduce a first charge injection of the first switch, and reduce a second charge injection of the second switch; and an output coupled to the first switch, the second switch, and the dummy component. A method comprises: providing an output from either a first switch or a second switch; coupling, by a dummy component, to the first switch and the second switch; using a BBM action; and reducing, by the dummy component, a first charge injection of the first switch or a second charge injection of the second switch.

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