Abstract:
A reference circuit may include a bandgap reference stage, a filter stage, and a buffer stage. The reference stage may be configured to generate a reference voltage or current. The filter stage may be coupled to the reference stage and may be configured to receive the reference voltage or current, filter noise from the reference voltage or current, receive a buffer output voltage or current, and filter noise from the buffer output voltage or current. The buffer stage may be coupled to the filter stage and may be configured to isolate the reference stage and the filter stage from a loading effect of a load circuit and generate a reference signal based on the reference voltage or current to drive the load circuit.
Abstract:
A circuit includes: a driver circuit; a sense resistor; a test circuit; a current sense circuit; a calibration controller; and a switch controller. The current sense circuit is configured to: obtain first sense signals responsive to a test voltage applied to the sense resistor by the test circuit, the test voltage being a direct-circuit voltage; and obtain second sense signals responsive a supply voltage applied to the sense resistor by the driver circuit, the supply voltage including a common-mode voltage. The calibration controller is configured to calibrate the current sense circuit responsive to the first sense signals and the second sense signals. The switch controller is configured to update switch control signals provided to the driver circuit responsive to current sense signals obtained by the calibrated current sense circuit.
Abstract:
A temperature dependent correction circuit includes a first supply source, a second supply source, a rectifying circuit, and a reference. The first supply source is configured to supply a first signal that varies with temperature along a first constant or continuously variable slope. The second supply source is configured to supply a second signal that varies with temperature along a second constant or continuously variable slope. The rectifying circuit is configured to receive the first and second signal, rectify the first signal to produce a first rectified signal, and add the first rectified signal to the second signal to produce a correction signal. The reference is configured to receive the correction signal.
Abstract:
An electrical device includes an integrated circuit having device circuitry and a boost converter coupled to the device circuitry. The boost converter includes a digital integrator circuit having: a first comparator; a second comparator; a counter configured to count up, count down, and pause based on a first output signal provided by the first comparator and based on a second output signal provided by the second comparator; and a digital-to-analog converter (DAC) configured to provide a feedback adjustment signal for the boost converter based on a count value provided by the counter.
Abstract:
A circuit includes a programmable gain amplifier (PGA) having a PGA output. The circuit further includes a delta-sigma modulator having an input coupled to the PGA output. The circuit also includes a digital filter and a dynamic range enhancer (DRE) circuit. The digital filter is coupled to the delta-sigma modulator output. The DRE circuit is coupled to the delta-sigma modulator output and to the PGA. The DRE circuit is configured to monitor a signal level of the delta-sigma modulator output. Responsive to the signal level being less than a DRE threshold, the DRE circuit is configured to program the PGA for a gain level greater than unity gain and to cause the digital filter to implement an attenuation of a same magnitude as the gain level to be programmed into the PGA.
Abstract:
In some examples, a circuit includes a first integrator having an input and an output. The circuit also includes a switching architecture having first and second terminals, the first terminal of the switching architecture coupled to the output of the first integrator. The circuit also includes a second integrator having an input and an output, the input of the second integrator coupled to the second terminal of the switching architecture. The circuit also includes a quantizer having an input and an output, the input of the quantizer coupled to the output of the second integrator. The circuit also includes a digital processing circuit having an input and an output, the input of the digital processing circuit coupled to the output of the quantizer.
Abstract:
A multiplexer comprises: a first switch; a second switch; a dummy component coupled to the first switch and the second switch and configured to: reduce a first charge injection of the first switch, and reduce a second charge injection of the second switch; and an output coupled to the first switch, the second switch, and the dummy component. A method comprises: providing an output from either a first switch or a second switch; coupling, by a dummy component, to the first switch and the second switch; using a BBM action; and reducing, by the dummy component, a first charge injection of the first switch or a second charge injection of the second switch.
Abstract:
In some examples, a circuit includes a first transistor having a control terminal and first and second terminals. The circuit also includes a first capacitor having first and second terminals, the first terminal of the first capacitor coupled to the control terminal of the first transistor and the second terminal of the first capacitor coupled to the second terminal of the first transistor. The circuit also includes a first switch having first and second terminals, the second terminal of the first switch coupled to the control terminal of the first transistor. The circuit also includes a second capacitor having first and second terminals, the first terminal of the second capacitor coupled to the first terminal of the first transistor and the second terminal of the second capacitor coupled to the first terminal of the first switch.
Abstract:
A circuit includes an analog-to-digital converter (ADC). The circuit also includes an analog front end (AFE) having an AFE input and an AFE output. The AFE output is coupled the ADC's input. The AFE includes a programmable gain amplifier (PGA) having a first PGA input and a second PGA input. The PGA includes a first operational amplifier (OP AMP) with first and second OPAMP inputs. The AFE also including a programmable resistance circuit having a first programmable resistance circuit input and first and second programmable resistance circuit outputs. The first programmable resistance circuit input is coupled to the first and second PGA inputs. The programmable resistance circuit includes a resistor network having first and second balance resistances. The first balance resistance is coupled to the first and second OP AMP inputs, and the second balance resistance is coupled to the first and second OP AMP inputs.
Abstract:
A multiplexer comprises: a first switch; a second switch; a dummy component coupled to the first switch and the second switch and configured to: reduce a first charge injection of the first switch, and reduce a second charge injection of the second switch; and an output coupled to the first switch, the second switch, and the dummy component. A method comprises: providing an output from either a first switch or a second switch; coupling, by a dummy component, to the first switch and the second switch; using a BBM action; and reducing, by the dummy component, a first charge injection of the first switch or a second charge injection of the second switch.