公开(公告)号：US20210232406A1

公开(公告)日：2021-07-29

申请号：US17209333

申请日：2021-03-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yogesh Vikram Marathe ,  Kedar Satish Chitnis ,  Rishabh Garg

IPC: G06F9/4401

Abstract: An embedded multiprocessor system is provided that includes a multiprocessor system on a chip (SOC), a memory coupled to the multiprocessor SOC, the memory storing application software partitioned into an initial boot stage and at least one additional boot stage, and a secondary boot loader configured to boot load the initial boot stage on at least one processor of the multiprocessor SOC, wherein the initial boot stage begins executing and flow of data from the initial boot stage to the at least one additional boot stage is disabled, wherein the application software is configured to boot load a second boot stage of the at least one additional boot stage on at least one other processor of the multiprocessor SOC and to enable flow of data between the initial boot stage and the second boot stage.

公开(公告)号：US20170123810A1

公开(公告)日：2017-05-04

申请号：US15087856

申请日：2016-03-31

Applicant: Texas Instruments Incorporated

Inventor： Yogesh Vikram Marathe ,  Kedar Satish Chitnis ,  Rishabh Garg

IPC: G06F9/44 ,  H04N5/225

CPC classification number: G06F9/4401 ,  G06F9/4405

Abstract: An embedded multiprocessor system is provided that includes a multiprocessor system on a chip (SOC), a memory coupled to the multiprocessor SOC, the memory storing application software partitioned into an initial boot stage and at least one additional boot stage, and a secondary boot loader configured to boot load the initial boot stage on at least one processor of the multiprocessor SOC, wherein the initial boot stage begins executing and flow of data from the initial boot stage to the at least one additional boot stage is disabled, wherein the application software is configured to boot load a second boot stage of the at least one additional boot stage on at least one other processor of the multiprocessor SOC and to enable flow of data between the initial boot stage and the second boot stage.

公开(公告)号：US11681534B2

公开(公告)日：2023-06-20

申请号：US17209333

申请日：2021-03-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yogesh Vikram Marathe ,  Kedar Satish Chitnis ,  Rishabh Garg

IPC: G06F9/4401

CPC classification number: G06F9/4401 ,  G06F9/4405

Abstract: An embedded multiprocessor system is provided that includes a multiprocessor system on a chip (SOC), a memory coupled to the multiprocessor SOC, the memory storing application software partitioned into an initial boot stage and at least one additional boot stage, and a secondary boot loader configured to boot load the initial boot stage on at least one processor of the multiprocessor SOC, wherein the initial boot stage begins executing and flow of data from the initial boot stage to the at least one additional boot stage is disabled, wherein the application software is configured to boot load a second boot stage of the at least one additional boot stage on at least one other processor of the multiprocessor SOC and to enable flow of data between the initial boot stage and the second boot stage.

公开(公告)号：US10956169B2

公开(公告)日：2021-03-23

申请号：US15087856

申请日：2016-03-31

Applicant: Texas Instruments Incorporated

Inventor： Yogesh Vikram Marathe ,  Kedar Satish Chitnis ,  Rishabh Garg

IPC: G06F9/4401

Abstract: An embedded multiprocessor system is provided that includes a multiprocessor system on a chip (SOC), a memory coupled to the multiprocessor SOC, the memory storing application software partitioned into an initial boot stage and at least one additional boot stage, and a secondary boot loader configured to boot load the initial boot stage on at least one processor of the multiprocessor SOC, wherein the initial boot stage begins executing and flow of data from the initial boot stage to the at least one additional boot stage is disabled, wherein the application software is configured to boot load a second boot stage of the at least one additional boot stage on at least one other processor of the multiprocessor SOC and to enable flow of data between the initial boot stage and the second boot stage.