公开(公告)号：US12050929B2

公开(公告)日：2024-07-30

申请号：US17123653

申请日：2020-12-16

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Niraj Nandan ,  Mihir Narendra Mody ,  Kedar Satish Chitnis

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4812 ,  G06F9/5027 ,  G06F2209/5018

Abstract: A data processing device is provided that includes a plurality of hardware data processing nodes, wherein each hardware data processing node performs a task, and a hardware thread scheduler including a plurality of hardware task schedulers configured to control execution of a respective task on a respective hardware data processing node of the plurality of hardware data processing nodes, and a proxy hardware task scheduler coupled to a data processing node external to the data processing device, wherein the proxy hardware task scheduler is configured to control execution of a task by the external data processing device, wherein the hardware thread scheduler is configurable to execute a thread of tasks, the tasks including the task controlled by the proxy hardware task scheduler and a first task controlled by a first hardware task scheduler of the plurality of hardware task schedulers.

公开(公告)号：US20230244557A1

公开(公告)日：2023-08-03

申请号：US18132683

申请日：2023-04-10

Applicant: Texas Instruments Incorporated

Inventor： Kedar Satish Chitnis ,  Charles Lance Fuoco ,  Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  William A. Mills ,  Gregory Raymond Shurtz ,  Amritpal Singh Mundra

IPC: G06F9/54 ,  G06F9/50 ,  G06F9/38 ,  G06F9/455 ,  G06F9/48

CPC classification number: G06F9/546 ,  G06F9/5027 ,  G06F9/3836 ,  G06F9/45558 ,  G06F9/4806 ,  G06F2009/45583 ,  G06F2009/45587

Abstract: This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.

公开(公告)号：US10908946B2

公开(公告)日：2021-02-02

申请号：US15396172

申请日：2016-12-30

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Niraj Nandan ,  Mihir Narendra Mody ,  Kedar Satish Chitnis

IPC: G06F9/48 ,  G06F9/50

Abstract: A data processing device is provided that includes a plurality of hardware data processing nodes, wherein each hardware data processing node performs a task, and a hardware thread scheduler including a plurality of hardware task schedulers configured to control execution of a respective task on a respective hardware data processing node of the plurality of hardware data processing nodes, and a proxy hardware task scheduler coupled to a data processing node external to the data processing device, wherein the proxy hardware task scheduler is configured to control execution of a task by the external data processing device, wherein the hardware thread scheduler is configurable to execute a thread of tasks, the tasks including the task controlled by the proxy hardware task scheduler and a first task controlled by a first hardware task scheduler of the plurality of hardware task schedulers.

公开(公告)号：US20170123810A1

公开(公告)日：2017-05-04

申请号：US15087856

申请日：2016-03-31

Applicant: Texas Instruments Incorporated

Inventor： Yogesh Vikram Marathe ,  Kedar Satish Chitnis ,  Rishabh Garg

IPC: G06F9/44 ,  H04N5/225

CPC classification number: G06F9/4401 ,  G06F9/4405

Abstract: An embedded multiprocessor system is provided that includes a multiprocessor system on a chip (SOC), a memory coupled to the multiprocessor SOC, the memory storing application software partitioned into an initial boot stage and at least one additional boot stage, and a secondary boot loader configured to boot load the initial boot stage on at least one processor of the multiprocessor SOC, wherein the initial boot stage begins executing and flow of data from the initial boot stage to the at least one additional boot stage is disabled, wherein the application software is configured to boot load a second boot stage of the at least one additional boot stage on at least one other processor of the multiprocessor SOC and to enable flow of data between the initial boot stage and the second boot stage.

公开(公告)号：US12111780B2

公开(公告)日：2024-10-08

申请号：US17677638

申请日：2022-02-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Ankur Ankur ,  Vivek Vilas Dhande ,  Kedar Satish Chitnis ,  Niraj Nandan ,  Brijesh Jadav ,  Shyam Jagannathan ,  Prithvi Shankar Yeyyadi Anantha ,  Santhanakrishnan Narayanan Narayanan

IPC: G06F13/28 ,  G06F9/48 ,  G06F13/16 ,  G06F13/42 ,  G06F15/78

CPC classification number: G06F13/28 ,  G06F9/4881 ,  G06F13/1673 ,  G06F13/4221 ,  G06F15/7807

Abstract: A system-on-chip (SoC) in which trace data is managed includes a first memory device, a first interface to couple the first memory to a second memory external to the system-on-chip, and a first processing resource coupled to the first interface and the first memory device. The first processing resource includes a data buffer and a first direct access memory (DMA) controller. The first DMA controller transmits data from the data buffer to the first interface over a first channel, and transmits the data from the data buffer with associated trace information for the data to the first memory device over a second channel.

公开(公告)号：US20210232406A1

公开(公告)日：2021-07-29

申请号：US17209333

申请日：2021-03-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yogesh Vikram Marathe ,  Kedar Satish Chitnis ,  Rishabh Garg

IPC: G06F9/4401

Abstract: An embedded multiprocessor system is provided that includes a multiprocessor system on a chip (SOC), a memory coupled to the multiprocessor SOC, the memory storing application software partitioned into an initial boot stage and at least one additional boot stage, and a secondary boot loader configured to boot load the initial boot stage on at least one processor of the multiprocessor SOC, wherein the initial boot stage begins executing and flow of data from the initial boot stage to the at least one additional boot stage is disabled, wherein the application software is configured to boot load a second boot stage of the at least one additional boot stage on at least one other processor of the multiprocessor SOC and to enable flow of data between the initial boot stage and the second boot stage.

公开(公告)号：US10929209B2

公开(公告)日：2021-02-23

申请号：US16377404

申请日：2019-04-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kedar Satish Chitnis ,  Charles Lance Fuoco ,  Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  William A. Mills ,  Gregory Raymond Shurtz ,  Amritpal Singh Mundra

IPC: G06F9/54 ,  G06F9/50 ,  G06F9/38 ,  G06F9/455 ,  G06F9/48

Abstract: This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.

公开(公告)号：US11656925B2

公开(公告)日：2023-05-23

申请号：US17138036

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Kedar Satish Chitnis ,  Charles Lance Fuoco ,  Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  William A. Mills ,  Gregory Raymond Shurtz ,  Amritpal Singh Mundra

IPC: G06F9/54 ,  G06F9/50 ,  G06F9/38 ,  G06F9/455 ,  G06F9/48

CPC classification number: G06F9/546 ,  G06F9/3836 ,  G06F9/45558 ,  G06F9/4806 ,  G06F9/5027 ,  G06F2009/45583 ,  G06F2009/45587

Abstract: This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.

公开(公告)号：US10956169B2

公开(公告)日：2021-03-23

申请号：US15087856

申请日：2016-03-31

Applicant: Texas Instruments Incorporated

Inventor： Yogesh Vikram Marathe ,  Kedar Satish Chitnis ,  Rishabh Garg

IPC: G06F9/4401

Abstract: An embedded multiprocessor system is provided that includes a multiprocessor system on a chip (SOC), a memory coupled to the multiprocessor SOC, the memory storing application software partitioned into an initial boot stage and at least one additional boot stage, and a secondary boot loader configured to boot load the initial boot stage on at least one processor of the multiprocessor SOC, wherein the initial boot stage begins executing and flow of data from the initial boot stage to the at least one additional boot stage is disabled, wherein the application software is configured to boot load a second boot stage of the at least one additional boot stage on at least one other processor of the multiprocessor SOC and to enable flow of data between the initial boot stage and the second boot stage.

公开(公告)号：US20180189105A1

公开(公告)日：2018-07-05

申请号：US15396153

申请日：2016-12-30

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Niraj Nandan ,  Mihir Narendra Mody ,  Kedar Satish Chitnis

IPC: G06F9/50 ,  G06F9/46

CPC classification number: G06F9/5027 ,  G06F9/4812 ,  G06F2209/5018

Abstract: A data processing device is provided that includes a plurality of hardware data processing nodes, wherein each hardware data processing node is configured to execute a task, and a hardware thread scheduler coupled to the plurality of hardware data processing nodes, the hardware thread scheduler configurable to concurrently execute a first thread of tasks and a second thread of tasks on the plurality of hardware data processing nodes.