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公开(公告)号：US07712062B2
公开(公告)日：2010-05-04
申请号：US12029440
申请日：2008-02-11
CPC分类号： G06F17/5031 , G01R31/30 , G06F17/5022
摘要： A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files.
摘要翻译： 包含至少两个时钟域的电路设计使用用于注入亚稳态效应的新型系统和方法进行模拟。 该系统包括检测器，用于在仿真期间当发送时钟域中的时钟和接收时钟域中的时钟对准时以及当接收时钟域交叉信号的寄存器的输入正在改变时进行检测。 该系统包括覆盖监测器，用于在模拟期间测量与亚稳态注入相关的统计。 在仿真期间的适当时间，系统准确地模拟亚稳态的影响，接收时域交叉信号的寄存器的伪随机反转输出。 通过准确地模拟亚稳态的影响，可以在模拟预先存在的模拟测试的同时检测电路设计中的误差。 具有亚稳态效应注入的模拟是可重复的，不需要修改预先存在的RTL设计文件或模拟测试文件。
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公开(公告)号：US07454728B2
公开(公告)日：2008-11-18
申请号：US11759888
申请日：2007-06-07
申请人： Tai An Ly , Ka Kei Kwok , Vijaya Vardhan Gupta , Ross Andrew Andersen , Ping Fai Yeung , Neil Patrick Hand , Lawrence Curtis Widdoes, Jr.
发明人： Tai An Ly , Ka Kei Kwok , Vijaya Vardhan Gupta , Ross Andrew Andersen , Ping Fai Yeung , Neil Patrick Hand , Lawrence Curtis Widdoes, Jr.
CPC分类号： G06F17/5022 , G01R31/30
摘要： During verification of a description of a circuit containing a pre-determined assertion, in order to detect incorrect behavior of the circuit that may be caused by metastability occurring in signals that cross clock domains (“CDC” signals) in the circuit, the description of the circuit is automatically transformed by addition of circuitry to inject the effects of metastability into the CDC signals. The transformed description containing the circuitry to inject metastability is verified in the normal manner. Certain embodiments analyze the transformed description using a model checking method to determine a stimulus sequence that will cause the pre-determined assertion to be violated. The transformed circuit is then simulated in some embodiments, using the stimulus sequence from model checking, and an incorrect behavior of the circuit due to metastability is displayed, for diagnosis by the circuit designer. The circuit designer may revise the circuit description and iterate as noted above.
摘要翻译： 在验证包含预定断言的电路的描述期间，为了检测可能由在电路中交叉时钟域（“CDC”信号）的信号中发生的亚稳态引起的电路的不正确行为，描述 该电路通过添加电路自动转换，以将亚稳态的影响注入到CDC信号中。 以正常方式验证包含注入亚稳态的电路的变换描述。 某些实施例使用模型检查方法分析变换的描述，以确定将导致预定的断言被违反的刺激序列。 在一些实施例中，使用来自模型检查的刺激序列来模拟变换电路，并且显示由于亚稳态引起的电路的错误行为，以供电路设计者进行诊断。 电路设计者可以修改电路描述并如上所述进行迭代。
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公开(公告)号：US07243322B1
公开(公告)日：2007-07-10
申请号：US10859055
申请日：2004-06-01
申请人： Tai An Ly , Ka Kei Kwok , Vijaya Vardhan Gupta , Ross Andrew Ander , Ping Fai Yeung , Neil Patrick Hand , Lawrence Curtis Widdoes, Jr.
发明人： Tai An Ly , Ka Kei Kwok , Vijaya Vardhan Gupta , Ross Andrew Ander , Ping Fai Yeung , Neil Patrick Hand , Lawrence Curtis Widdoes, Jr.
CPC分类号： G06F17/5022 , G01R31/30
摘要： During verification of a description of a circuit containing a pre-determined assertion, in order to detect incorrect behavior of the circuit that may be caused by metastability occurring in signals that cross clock domains (“CDC” signals) in the circuit, the description of the circuit is automatically transformed by addition of circuitry to inject the effects of metastability into the CDC signals. The transformed description containing the circuitry to inject metastability is verified in the normal manner. Certain embodiments analyze the transformed description using a model checking method to determine a stimulus sequence that will cause the pre-determined assertion to be violated. The transformed circuit is then simulated in some embodiments, using the stimulus sequence from model checking, and an incorrect behavior of the circuit due to metastability is displayed, for diagnosis by the circuit designer. The circuit designer may revise the circuit description and iterate as noted above.
摘要翻译： 在验证包含预定断言的电路的描述期间，为了检测可能由在电路中交叉时钟域（“CDC”信号）的信号中发生的亚稳态引起的电路的不正确行为，描述 该电路通过添加电路自动转换，以将亚稳态的影响注入到CDC信号中。 以正常方式验证包含注入亚稳态的电路的变换描述。 某些实施例使用模型检查方法分析变换的描述，以确定将导致预定的断言被违反的刺激序列。 在一些实施例中，使用来自模型检查的刺激序列来模拟变换电路，并且显示由于亚稳态引起的电路的错误行为，以供电路设计者进行诊断。 电路设计者可以修改电路描述并如上所述进行迭代。
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公开(公告)号：US08438516B2
公开(公告)日：2013-05-07
申请号：US12773462
申请日：2010-05-04
CPC分类号： G06F17/5031 , G01R31/30 , G06F17/5022
摘要： A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files.
摘要翻译： 包含至少两个时钟域的电路设计使用用于注入亚稳态效应的新型系统和方法进行模拟。 该系统包括检测器，用于在仿真期间当发送时钟域中的时钟和接收时钟域中的时钟对准时以及当接收时钟域交叉信号的寄存器的输入正在改变时进行检测。 该系统包括覆盖监测器，用于在模拟期间测量与亚稳态注入相关的统计。 在仿真期间的适当时间，系统准确地模拟亚稳态的影响，接收时域交叉信号的寄存器的伪随机反转输出。 通过准确地模拟亚稳态的影响，可以在模拟预先存在的模拟测试的同时检测电路设计中的误差。 具有亚稳态效应注入的模拟是可重复的，不需要修改预先存在的RTL设计文件或模拟测试文件。
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公开(公告)号：US20100287524A1
公开(公告)日：2010-11-11
申请号：US12773462
申请日：2010-05-04
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G01R31/30 , G06F17/5022
摘要： A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files.
摘要翻译： 包含至少两个时钟域的电路设计使用用于注入亚稳态效应的新型系统和方法进行模拟。 该系统包括检测器，用于在仿真期间当发送时钟域中的时钟和接收时钟域中的时钟对准时以及当接收时钟域交叉信号的寄存器的输入正在改变时进行检测。 该系统包括覆盖监测器，用于在模拟期间测量与亚稳态注入相关的统计。 在仿真期间的适当时间，系统准确地模拟亚稳态的影响，接收时域交叉信号的寄存器的伪随机反转输出。 通过准确地模拟亚稳态的影响，可以在模拟预先存在的模拟测试的同时检测电路设计中的误差。 具有亚稳态效应注入的模拟是可重复的，不需要修改预先存在的RTL设计文件或模拟测试文件。
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公开(公告)号：US07356789B2
公开(公告)日：2008-04-08
申请号：US11140678
申请日：2005-05-27
CPC分类号： G06F17/5031 , G01R31/30 , G06F17/5022
摘要： A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files.
摘要翻译： 包含至少两个时钟域的电路设计使用用于注入亚稳态效应的新型系统和方法进行模拟。 该系统包括检测器，用于在仿真期间当发送时钟域中的时钟和接收时钟域中的时钟对准时以及当接收时钟域交叉信号的寄存器的输入正在改变时进行检测。 该系统包括覆盖监测器，用于在模拟期间测量与亚稳态注入相关的统计。 在仿真期间的适当时间，系统准确地模拟亚稳态的影响，接收时域交叉信号的寄存器的伪随机反转输出。 通过准确地模拟亚稳态的影响，可以在模拟预先存在的模拟测试的同时检测电路设计中的误差。 具有亚稳态效应注入的模拟是可重复的，不需要修改预先存在的RTL设计文件或模拟测试文件。
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公开(公告)号：US20080134115A1
公开(公告)日：2008-06-05
申请号：US12029440
申请日：2008-02-11
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G01R31/30 , G06F17/5022
摘要： A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files.
摘要翻译： 包含至少两个时钟域的电路设计使用用于注入亚稳态效应的新型系统和方法进行模拟。 该系统包括检测器，用于在仿真期间当发送时钟域中的时钟和接收时钟域中的时钟对准时以及当接收时钟域交叉信号的寄存器的输入正在改变时进行检测。 该系统包括覆盖监测器，用于在模拟期间测量与亚稳态注入相关的统计。 在仿真期间的适当时间，系统准确地模拟亚稳态的影响，接收时域交叉信号的寄存器的伪随机反转输出。 通过准确地模拟亚稳态的影响，可以在模拟预先存在的模拟测试的同时检测电路设计中的误差。 具有亚稳态效应注入的模拟是可重复的，不需要修改预先存在的RTL设计文件或模拟测试文件。
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