公开(公告)号：US20250040183A1

公开(公告)日：2025-01-30

申请号：US18361051

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao CHANG ,  Wei-Yang LEE ,  Kuan-Hao CHENG ,  Cheng-Yi PENG

IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A method includes: forming a stack of semiconductor nanostructures on a semiconductor fin; forming a source/drain opening adjacent the stack; forming a bottom dielectric layer on the semiconductor fin; forming a source/drain region in the source/drain opening, a void being present between the source/drain region and the bottom dielectric layer; forming a dielectric layer on the source/drain region; forming a hardened portion of the dielectric layer by treating the dielectric layer, the hardened portion having higher etch selectivity than other portions of the dielectric layer; removing the other portions of the dielectric layer, exposing the void; forming a source/drain contact opening that extends to and connects with the void, the source/drain contact opening exposing sidewalls of the source/drain region; forming a liner layer on exposed surfaces of the source/drain region; and forming a conductive core layer on the liner layer, the conductive core layer being in contact with the liner layer on a top surface, sidewalls and a bottom surface of the source/drain region.