公开(公告)号：US20250022931A1

公开(公告)日：2025-01-16

申请号：US18779444

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Yeh CHEN ,  Wei-Yang LEE ,  Chia-Pin LIN ,  Da-Wen LIN

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: Gate spacer that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a gate stack disposed over a semiconductor layer and a gate spacer disposed on a sidewall of the gate stack. A source/drain feature is disposed in the semiconductor layer and adjacent the gate spacer. A low-k contact etch stop layer is disposed on a top surface and a sidewall of the gate spacer and a portion of the gate spacer is disposed between the low-k contact etch stop layer and the semiconductor layer. A source/drain contact is disposed on the source/drain feature and adjacent the low-k contact etch stop layer.

公开(公告)号：US20190097006A1

公开(公告)日：2019-03-28

申请号：US16101897

申请日：2018-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kun-Mu LI ,  Wei-Yang LEE ,  Wen-Chu HSIAO

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/78 ,  H01L29/08 ,  H01L29/16 ,  H01L29/66 ,  H01L29/40 ,  H01L21/8234

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a first source/drain structure, and a contact structure. The gate structure has a gate dielectric layer over a first fin structure. The first source/drain structure is positioned in the first fin structure and adjacent to the gate structure. The first source/drain structure includes a first epitaxial layer in contact with the top surface of the first fin structure and a second epitaxial layer over the first epitaxial layer and extending above a bottom surface of the gate dielectric layer. The contact structure extends into the first source/drain structure. The top surface of the first fin structure is between a top surface and a bottom surface of the first source/drain structure.

公开(公告)号：US20210273079A1

公开(公告)日：2021-09-02

申请号：US16949446

申请日：2021-01-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching CHU ,  Wei-Yang LEE ,  Feng-Cheng YANG ,  Yen-Ming CHEN

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: Methods and devices formed thereof that include a fin structure extending from a substrate and a gate structure is formed over the fin structure. An epitaxial feature is formed over the fin structure adjacent the gate structure. The epitaxial feature can include a hollow region (or dielectric filled hollow region) in the epitaxial source/drain region. A selective etching process is performed to remove at least a portion of an epitaxial region having a second dopant type to form the hollow area between the first epitaxial portion and the third epitaxial portion.

公开(公告)号：US20210118749A1

公开(公告)日：2021-04-22

申请号：US17113209

申请日：2020-12-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Bo-Yu LAI ,  Kai-Hsuan LEE ,  Wei-Yang LEE ,  Feng-Cheng YANG ,  Yen-Ming CHEN

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8234

Abstract: A semiconductor device includes a gate stack, an epitaxy structure, a first spacer, a second spacer, and a dielectric residue. The gate stack is over a substrate. The epitaxy structure is formed raised above the substrate. The first spacer is on a sidewall of the gate stack. The first spacer and the epitaxy structure define an air gap therebetween. The second spacer seals the air gap between the first spacer and the epitaxy structure. The dielectric residue is in the air gap and has an upper portion and a lower portion under the upper portion. The upper portion of the dielectric residue has higher etch resistance to phosphoric acid than that of the lower portion of the dielectric residue.

公开(公告)号：US20200027793A1

公开(公告)日：2020-01-23

申请号：US16585859

申请日：2019-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang LEE ,  Feng-Cheng YANG ,  Ting-Yeh CHEN

IPC: H01L21/8234 ,  H01L21/308 ,  H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure and a dielectric layer disposed on an upper surface of the isolation insulating layer. Both the first fin structure and the second fin structure are disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The first and second fin structures not covered by the gate structure are recessed below the upper surface of the isolation insulating layer. The source/drain structure is formed over the recessed first and second fin structures. A void is formed between the source/drain structure and the dielectric layer.

公开(公告)号：US20180102292A1

公开(公告)日：2018-04-12

申请号：US15830859

申请日：2017-12-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang LEE ,  Feng-Cheng YANG ,  Ting-Yeh CHEN

IPC: H01L21/8234 ,  H01L29/08 ,  H01L27/088 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/823425 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure and a dielectric layer disposed on an upper surface of the isolation insulating layer. Both the first fin structure and the second fin structure are disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The first and second fin structures not covered by the gate structure are recessed below the upper surface of the isolation insulating layer. The source/drain structure is formed over the recessed first and second fin structures. A void is formed between the source/drain structure and the dielectric layer.

公开(公告)号：US20160163820A1

公开(公告)日：2016-06-09

申请号：US15016214

申请日：2016-02-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang LEE ,  Ting-Yeh CHEN

IPC: H01L29/66 ,  H01L21/285 ,  H01L21/311

CPC classification number: H01L29/6681 ,  H01L21/2855 ,  H01L21/28556 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7851

Abstract: A method for manufacturing a FinFET, and FinFETs are provided. In various embodiments, the method for manufacturing a FinFET includes forming a fin structure over a substrate. Next, a dummy gate is deposited across over the fin structure. The method continues with forming a pair of first spacers on sidewalls of the dummy gate. Then, a source/drain region is formed in the fin structure not covered by the dummy gate. The method further includes removing the dummy gate to expose the fin structure. After that, the first spacers are truncated, and a gate stack is formed to cover the exposed fin structure and top surfaces of the first spacers.

Abstract translation: 提供一种制造FinFET和FinFET的方法。 在各种实施例中，制造FinFET的方法包括在衬底上形成翅片结构。 接下来，跨越翅片结构沉积虚拟栅极。 该方法继续在伪栅极的侧壁上形成一对第一间隔物。 然后，在未被虚拟栅极覆盖的鳍结构中形成源极/漏极区域。 该方法还包括去除伪栅极以暴露翅片结构。 之后，第一间隔件被截断，并且形成一个栅叠层以覆盖暴露的散热片结构和第一间隔件的顶表面。

公开(公告)号：US20250040183A1

公开(公告)日：2025-01-30

申请号：US18361051

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao CHANG ,  Wei-Yang LEE ,  Kuan-Hao CHENG ,  Cheng-Yi PENG

IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A method includes: forming a stack of semiconductor nanostructures on a semiconductor fin; forming a source/drain opening adjacent the stack; forming a bottom dielectric layer on the semiconductor fin; forming a source/drain region in the source/drain opening, a void being present between the source/drain region and the bottom dielectric layer; forming a dielectric layer on the source/drain region; forming a hardened portion of the dielectric layer by treating the dielectric layer, the hardened portion having higher etch selectivity than other portions of the dielectric layer; removing the other portions of the dielectric layer, exposing the void; forming a source/drain contact opening that extends to and connects with the void, the source/drain contact opening exposing sidewalls of the source/drain region; forming a liner layer on exposed surfaces of the source/drain region; and forming a conductive core layer on the liner layer, the conductive core layer being in contact with the liner layer on a top surface, sidewalls and a bottom surface of the source/drain region.

公开(公告)号：US20230369490A1

公开(公告)日：2023-11-16

申请号：US18346480

申请日：2023-07-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang LEE ,  Ting-Yeh CHEN ,  Chii-Horng LI ,  Feng-Cheng YANG

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/0847

Abstract: A method includes forming a fin in a substrate. The fin is etched to create a source/drain recess. A source/drain feature is formed in the source/drain recess, in which a lattice constant of the source/drain feature is greater than a lattice constant of the fin. An epitaxy coat is grown over the source/drain feature, in which a lattice constant of the epitaxy coat is smaller than a lattice constant of the fin.

公开(公告)号：US20220384654A1

公开(公告)日：2022-12-01

申请号：US17818230

申请日：2022-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching CHU ,  Wei-Yang LEE ,  Feng-Cheng YANG ,  Yen-Ming CHEN

IPC: H01L29/78 ,  H01L29/08

Abstract: Methods and devices formed thereof that include a fin structure extending from a substrate and a gate structure is formed over the fin structure. An epitaxial feature is formed over the fin structure adjacent the gate structure. The epitaxial feature can include a hollow region (or dielectric filled hollow region) in the epitaxial source/drain region. A selective etching process is performed to remove at least a portion of an epitaxial region having a second dopant type to form the hollow area between the first epitaxial portion and the third epitaxial portion.