公开(公告)号：US20240079483A1

公开(公告)日：2024-03-07

申请号：US18124980

申请日：2023-03-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hung LIN ,  I-Hsieh WONG ,  Tzu-Hua CHIU ,  Cheng-Yi PENG ,  Chia-Pin LIN

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66439

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a fin base disposed on the substrate, nanostructured channel regions disposed on a first portion of the fin base, a gate structure surrounding the nanostructured channel regions, a source/drain (S/D) region disposed on a second portion of the fin base, and an isolation structure disposed between the S/D region and the second portion of the fin base. The isolation structure includes an undoped semiconductor layer disposed on the second portion of the fin base, a silicon-rich dielectric layer disposed on the undoped semiconductor layer, and an air spacer disposed on the silicon-rich dielectric layer.

公开(公告)号：US20220238523A1

公开(公告)日：2022-07-28

申请号：US17718182

申请日：2022-04-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi PENG ,  Chun-Chieh LU ,  Meng-Hsuan HSIAO ,  Ling-Yen YEH ,  Carlos H. DIAZ ,  Tung-Ying LEE

IPC: H01L27/092 ,  H01L23/532 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L29/08 ,  H01L29/417 ,  H01L21/768 ,  H01L21/02 ,  H01L23/538 ,  H01L29/423 ,  H01L29/778 ,  H01L29/45 ,  H01L27/12 ,  H01L29/06 ,  G06F16/955 ,  G06F3/0481 ,  G06F13/00 ,  H04L9/40 ,  H04L67/303 ,  H04L67/306

Abstract: In a method for forming an integrated semiconductor device, a first inter-layer dielectric (ILD) layer is formed over a semiconductor device that includes a first transistor structure, a two-dimensional (2D) material layer is formed over and in contact with the first ILD layer, the 2D material layer is patterned to form a channel layer of a second transistor structure, a source electrode and a drain electrode of the second transistor structure are formed over the patterned 2D material layer and laterally spaced apart from each other, a gate dielectric layer of the second transistor structure is formed over the patterned 2D material layer, the source electrode and the drain electrode, and a gate electrode of the second transistor structure is formed over the gate dielectric layer and laterally between the source electrode and the drain electrode.

公开(公告)号：US20220208986A1

公开(公告)日：2022-06-30

申请号：US17654807

申请日：2022-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung TSAI ,  Cheng-Yi PENG ,  Yin-Pin WANG ,  Kuo-Feng YU ,  Da-Wen LIN ,  Jian-Hao CHEN ,  Shahaji B. MORE

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/324 ,  H01L21/768 ,  H01L21/223 ,  H01L21/8234

Abstract: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.

公开(公告)号：US20210005734A1

公开(公告)日：2021-01-07

申请号：US17026562

申请日：2020-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh LU ,  Carlos H. DIAZ ,  Chih-Sheng CHANG ,  Cheng-Yi PENG ,  Ling-Yen YEH

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/324 ,  H01L21/02 ,  H01L49/02 ,  H01L29/66 ,  H01L21/28

Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.

公开(公告)号：US20200303549A1

公开(公告)日：2020-09-24

申请号：US16898659

申请日：2020-06-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung TSAI ,  Shahaji B. MORE ,  Cheng-Yi PENG ,  Yu-Ming LIN ,  Kuo-Feng YU ,  Ziwei FANG

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L29/45 ,  H01L29/165 ,  H01L27/088 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/06

Abstract: A method for forming a FinFET device structure is provided. The method includes forming a fin structure extended above a substrate and forming a gate structure formed over a portion of the fin structure. The method also includes forming a source/drain (S/D) structure over the fin structure, and the S/D structure is adjacent to the gate structure. The method further includes doping an outer portion of the S/D structure to form a doped region, and the doped region includes gallium (Ga). The method includes forming a metal silicide layer over the doped region; and forming an S/D contact structure over the metal silicide layer.

公开(公告)号：US20200168716A1

公开(公告)日：2020-05-28

申请号：US16590220

申请日：2019-10-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi PENG ,  Wen-Hsing HSIEH ,  Wen-Yuan CHEN ,  Jon-Hsu HO ,  Song-Bor LEE ,  Bor-Zen TIEN

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/16 ,  H01L29/24 ,  H01L29/08 ,  H01L29/786 ,  H01L21/02

Abstract: A semiconductor device includes a channel region, a source/drain region adjacent to the channel region, and a source/drain epitaxial layer. The source/drain epitaxial layer includes a first epitaxial layer epitaxially formed on the source/drain region, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer. The first epitaxial layer includes at least one selected from the group consisting of a SiAs layer, a SiC layer and a SiCP layer.

公开(公告)号：US20200033388A1

公开(公告)日：2020-01-30

申请号：US16588654

申请日：2019-09-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi PENG ,  Chia-Cheng HO ,  Ming-Shiang LIN ,  Chih-Sheng CHANG ,  Carlos H. DIAZ

IPC: G01R27/16 ,  H01L21/66

Abstract: A semiconductor test device for measuring a contact resistance includes: first fin structures, upper portions of the first fin structures protruding from an isolation insulating layer; epitaxial layers formed on the upper portions of the first fin structures, respectively; first conductive layers formed on the epitaxial layers, respectively; a first contact layer disposed on the first conductive layers at a first point; a second contact layer disposed on the first conductive layers at a second point apart from the first point; a first pad coupled to the first contact layer via a first wiring; and a second pad coupled to the second contact layer via a second wiring. The semiconductor test device is configured to measure the contact resistance between the first contact layer and the first fin structures by applying a current between the first pad and the second pad.

公开(公告)号：US20190165143A1

公开(公告)日：2019-05-30

申请号：US15994691

申请日：2018-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. MORE ,  Chun-Hsiung TSAI ,  Cheng-Yi PENG ,  Shih-Chieh CHANG ,  Kuo-Feng YU

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L21/762

CPC classification number: H01L29/66492 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7833 ,  H01L29/7851

Abstract: Methods for forming semiconductor structures are provided. The method includes forming a fin structure over a substrate and forming a gate structure across the fin structure. The method further includes forming a fin spacer on a sidewall of the fin structure and partially removing the fin spacer. The method further includes recessing the fin structure to form a recess and implanting dopants from the recess to form a doped region. The method further includes diffusing the dopants in the doped region to form an expanded doped region and forming a source/drain structure over the expanded doped region.

公开(公告)号：US20190131420A1

公开(公告)日：2019-05-02

申请号：US15908348

申请日：2018-02-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh LU ,  Carlos H. DIAZ ,  Chih-Sheng CHANG ,  Cheng-Yi PENG ,  Ling-Yen YEH

IPC: H01L29/51 ,  H01L29/78 ,  H01L49/02 ,  H01L21/324 ,  H01L21/02

Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.

公开(公告)号：US20210175342A1

公开(公告)日：2021-06-10

申请号：US17179954

申请日：2021-02-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh LU ,  Cheng-Yi PENG ,  Chien-Hsing LEE ,  Ling-Yen YEH ,  Chih-Sheng CHANG ,  Carlos H. DIAZ

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L29/51 ,  H01L29/94

Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase.