公开(公告)号：US09001570B1

公开(公告)日：2015-04-07

申请号：US14040297

申请日：2013-09-27

Applicant: Texas Instruments Incorporated

Inventor： Rashmi Sachan ,  Parvinder Rana ,  Abhishek Kesarwani ,  Robert Pitts

IPC: G11C8/00 ,  G11C11/418 ,  G11C11/417 ,  G11C11/24

CPC classification number: G11C11/418 ,  G11C8/06 ,  G11C8/12 ,  G11C8/18 ,  G11C11/24 ,  G11C11/417

Abstract: A memory configurable to be used in an RTA mode includes an input latch configured to receive an input address bus and to generate a latched address bus that corresponds to a memory location. An address flop is configured to save the latched address and to generate a flopped address. A first block address pre-decoder stage is configured to generate a pre-decoded latched address to an RTA generation logic in response to the latched address bus; and a second block address pre-decoder configured to generate a pre-decoded flopped address to the RTA generation logic in response to the flopped address. The RTA generation logic generates an RTA enable signal one clock cycle before a memory block access, to activate a memory block corresponding to the memory location, such that an array supply voltage of the memory block starts charging one clock cycle before a memory block access.

Abstract translation: 可配置为在RTA模式中使用的存储器包括被配置为接收输入地址总线并且产生对应于存储器位置的锁存地址总线的输入锁存器。 地址触发器配置为保存锁存的地址并生成翻转的地址。 第一块地址预解码器级被配置为响应于锁存的地址总线而向RTA生成逻辑生成预解码的锁存地址; 以及第二块地址预解码器，其被配置为响应于所述经翻转的地址，向所述RTA生成逻辑生成预解码的翻转地址。 RTA生成逻辑在存储器块访问之前一个时钟周期产生RTA使能信号，以激活对应于存储器位置的存储器块，使得存储器块的阵列电源电压在存储器块访问之前开始一个时钟周期的充电。

公开(公告)号：US20140010032A1

公开(公告)日：2014-01-09

申请号：US13898803

申请日：2013-05-21

Applicant: Texas Instruments Incorporated

Inventor： Anand Seshadri ,  Dharin Shah ,  Parvinder Rana ,  Wah Kit Loh

IPC: G11C7/12 ,  G11C8/08

CPC classification number: G11C7/12 ,  G11C7/08 ,  G11C7/227 ,  G11C8/08

Abstract: A static random-access memory (SRAM) in an integrated circuit with circuitry for timing the enabling of sense amplifiers. The memory includes read/write SRAM cells, along with word-line tracking transistors arranged in one or more rows along a side of the read/write cells, and read-tracking transistors arranged in a column along a side of the read/write cells. A reference word line extends over the word-line tracking transistors, with its far end from the driver connected to pass transistors in the read-tracking transistors. The read-tracking transistors are preset to a known data state that, when accessed responsive to the reference word line, discharges a reference bit line, which in turn drives a sense amplifier enable signal.

Abstract translation: 集成电路中的静态随机存取存储器（SRAM），其具有用于定时使能读出放大器的电路。 存储器包括读/写SRAM单元以及排列在读/写单元侧的一行或多行的字线跟踪晶体以及沿着读/写单元的一侧排列在列中的读取 - 跟踪晶体管 。 参考字线延伸在字线跟踪晶体管上，其远端与驱动器连接，以在读取跟踪晶体管中传递晶体管。 读取跟踪晶体管被预设为已知数据状态，当响应于参考字线访问时，放电参考位线，该参考位线又驱动读出放大器使能信号。

公开(公告)号：US09576621B2

公开(公告)日：2017-02-21

申请号：US13898803

申请日：2013-05-21

Applicant: Texas Instruments Incorporated

Inventor： Anand Seshadri ,  Dharin Shah ,  Parvinder Rana ,  Wah Kit Loh

IPC: G11C7/12 ,  G11C8/08 ,  G11C7/08 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C7/08 ,  G11C7/227 ,  G11C8/08

Abstract: A static random-access memory (SRAM) in an integrated circuit with circuitry for timing the enabling of sense amplifiers. The memory includes read/write SRAM cells, along with word-line tracking transistors arranged in one or more rows along a side of the read/write cells, and read-tracking transistors arranged in a column along a side of the read/write cells. A reference word line extends over the word-line tracking transistors, with its far end from the driver connected to pass transistors in the read-tracking transistors. The read-tracking transistors are preset to a known data state that, when accessed responsive to the reference word line, discharges a reference bit line, which in turn drives a sense amplifier enable signal.

Abstract translation: 集成电路中的静态随机存取存储器（SRAM），其具有用于定时使能读出放大器的电路。 存储器包括读/写SRAM单元以及排列在读/写单元侧的一行或多行的字线跟踪晶体以及沿着读/写单元的一侧排列在列中的读取 - 跟踪晶体管 。 参考字线延伸在字线跟踪晶体管上，其远端与驱动器连接，以在读取跟踪晶体管中传递晶体管。 读取跟踪晶体管被预设为已知数据状态，当响应于参考字线访问时，放电参考位线，该参考位线又驱动读出放大器使能信号。

公开(公告)号：US20150092475A1

公开(公告)日：2015-04-02

申请号：US14040297

申请日：2013-09-27

Applicant: Texas Instruments Incorporated

Inventor： Rashmi Sachan ,  Parvinder Rana ,  Abhishek Kesarwani ,  Robert Pitts

IPC: G11C11/418

CPC classification number: G11C11/418 ,  G11C8/06 ,  G11C8/12 ,  G11C8/18 ,  G11C11/24 ,  G11C11/417

Abstract: A memory configurable to be used in an RTA mode includes an input latch configured to receive an input address bus and to generate a latched address bus that corresponds to a memory location. An address flop is configured to save the latched address and to generate a flopped address. A first block address pre-decoder stage is configured to generate a pre-decoded latched address to an RTA generation logic in response to the latched address bus; and a second block address pre-decoder configured to generate a pre-decoded flopped address to the RTA generation logic in response to the flopped address. The RTA generation logic generates an RTA enable signal one clock cycle before a memory block access, to activate a memory block corresponding to the memory location, such that an array supply voltage of the memory block starts charging one clock cycle before a memory block access.

Abstract translation: 可配置为在RTA模式中使用的存储器包括被配置为接收输入地址总线并且产生对应于存储器位置的锁存地址总线的输入锁存器。 地址触发器配置为保存锁存的地址并生成翻转的地址。 第一块地址预解码器级被配置为响应于锁存的地址总线而向RTA生成逻辑生成预解码的锁存地址; 以及第二块地址预解码器，其被配置为响应于所述经翻转的地址，向所述RTA生成逻辑生成预解码的翻转地址。 RTA生成逻辑在存储器块访问之前一个时钟周期产生RTA使能信号，以激活对应于存储器位置的存储器块，使得存储器块的阵列电源电压在存储器块访问之前开始一个时钟周期的充电。