WIRELESS NETWORK SYSTEMS
    2.
    发明申请
    WIRELESS NETWORK SYSTEMS 审中-公开
    无线网络系统

    公开(公告)号:US20130156016A1

    公开(公告)日:2013-06-20

    申请号:US13713374

    申请日:2012-12-13

    CPC classification number: H04W72/0406 H04W56/00 H04W84/12

    Abstract: Several wireless network systems are disclosed. In an embodiment, a wireless network system includes at least two access points and a distributed set of devices communicatively associated with the at least two access points. Each device from among the distributed set of devices comprises a pair of wireless stations and each wireless station from among the pair of wireless stations is configured to transmit data associated with an alert situation to a distinct access point from among the at least two access points. A communication between one or more access points from among the at least two access points and one or more wireless stations from among the pairs of wireless stations corresponding to the distributed set of devices is synchronized based on a timing synchronization information shared by at least two basic service sets (BSSs) corresponding to the at least two access points.

    Abstract translation: 公开了几种无线网络系统。 在一个实施例中,无线网络系统包括至少两个接入点和与该至少两个接入点通信地相关联的一组分布式设备。 所述分布式设备组中的每个设备包括一对无线站,并且所述一对无线站中的每个无线站被配置为将与警报情况相关联的数据从所述至少两个接入点中传送到不同接入点。 基于由至少两个基本信息共享的定时同步信息来同步来自所述至少两个接入点中的一个或多个接入点与对应于分布式设备组的无线电台对中的一个或多个无线电台之间的通信 对应于至少两个接入点的服务集(BSS)。

    APPARATUS FOR PRECISE TIMESTAMPING OF START OF ETHERNET FRAME

    公开(公告)号:US20240322927A1

    公开(公告)日:2024-09-26

    申请号:US18346019

    申请日:2023-06-30

    CPC classification number: H04J3/0664 H04J3/0682

    Abstract: Systems, apparatus, articles of manufacture, and methods are described for precise timestamping of an Ethernet frame. In some implementations, a device may include network interface circuitry; logic circuitry configured to execute instructions to cause the logic circuitry to: determine a first delay introduced by a physical coding sublayer circuitry at a first time; adjust a first timestamp associated with a first transmission based on the first delay, the first timestamp transmitted with the first transmission; determine a second delay introduced by the physical coding sublayer circuitry at a second time, the second delay different than the first delay; and adjust a second timestamp associated with a second transmission based on the second delay, the second timestamp transmitted with the second transmission.

    Dynamic processor-memory revectoring architecture
    4.
    发明授权
    Dynamic processor-memory revectoring architecture 有权
    动态处理器内存尊敬架构

    公开(公告)号:US09436617B2

    公开(公告)日:2016-09-06

    申请号:US14105852

    申请日:2013-12-13

    CPC classification number: G06F12/1081 G06F12/023 G06F2003/0697

    Abstract: A global navigation satellite system (GNSS) includes an efficient memory sharing architecture that provides additional search capacity by, e.g., sharing a portion of GNSS receiver processor memory with a general processor. A memory management unit dynamically revectors memory accesses in accordance with the various states of the GNSS receiver processor and arranging the available memory as a shared memory bank that can be efficiently shared between the general processor and the GNSS receiver processor. An optional ancillary memory system can provide additional memory to the general processor when the GNSS receiver processor has allocated memory that the general processor would otherwise use.

    Abstract translation: 全球导航卫星系统(GNSS)包括有效的存储器共享架构,其通过例如与一般处理器共享一部分GNSS接收机处理器存储器来提供额外的搜索能力。 存储器管理单元根据GNSS接收器处理器的各种状态动态地观察存储器访问,并将可用存储器布置为可在通用处理器和GNSS接收器处理器之间有效共享的共享存储器组。 当GNSS接收机处理器分配了通用处理器将另外使用的存储器时,可选的辅助存储器系统可以向通用处理器提供额外的存储器。

    DYNAMIC PROCESSOR-MEMORY REVECTORING ARCHITECTURE
    6.
    发明申请
    DYNAMIC PROCESSOR-MEMORY REVECTORING ARCHITECTURE 有权
    动态处理器 - 存储器反向架构

    公开(公告)号:US20150169223A1

    公开(公告)日:2015-06-18

    申请号:US14105852

    申请日:2013-12-13

    CPC classification number: G06F12/1081 G06F12/023 G06F2003/0697

    Abstract: A global navigation satellite system (GNSS) includes an efficient memory sharing architecture that provides additional search capacity by, e.g., sharing a portion of GNSS receiver processor memory with a general processor. A memory management unit dynamically revectors memory accesses in accordance with the various states of the GNSS receiver processor and arranging the available memory as a shared memory bank that can be efficiently shared between the general processor and the GNSS receiver processor. An optional ancillary memory system can provide additional memory to the general processor when the GNSS receiver processor has allocated memory that the general processor would otherwise use.

    Abstract translation: 全球导航卫星系统(GNSS)包括有效的存储器共享架构,其通过例如与一般处理器共享一部分GNSS接收机处理器存储器来提供额外的搜索能力。 存储器管理单元根据GNSS接收器处理器的各种状态动态地观察存储器访问,并将可用存储器布置为可在通用处理器和GNSS接收器处理器之间有效共享的共享存储器组。 当GNSS接收机处理器分配了通用处理器将另外使用的存储器时,可选的辅助存储器系统可以向通用处理器提供额外的存储器。

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