公开(公告)号：US10340899B2

公开(公告)日：2019-07-02

申请号：US15715290

申请日：2017-09-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Soman Purushothaman ,  Keshav Bhaktavatson Chintamani

IPC: H03K3/037 ,  H03K3/356 ,  H03K3/3562

Abstract: This invention is a retention circuit retaining the state of a circuit node driven by a primary drive circuit. This circuit includes cross coupled first and second inverters and a transmission gate. The transmission gate receives a retention mode signal and isolates the retention circuit and the circuit node when a retention mode is active and connects the retention circuit and the circuit node when the retention mode is inactive. In the preferred embodiment the primary drive circuit is constructed of transistors having a standard voltage threshold and the retention circuit is constructed of transistors having a high voltage threshold greater than said standard voltage threshold. A tristate inverter isolates the retention circuit from the circuit node when not in retention mode and supplies an inverse of a signal from output of said first inverter when in retention mode.

公开(公告)号：US20200212896A1

公开(公告)日：2020-07-02

申请号：US16236330

申请日：2018-12-28

Applicant: Texas Instruments Incorporated

Inventor： Soman Purushothaman ,  Sankar Prasad Debnath ,  Per Torstein Roine ,  Steven C. Bartling ,  Keshav Bhaktavatson Chintamani

IPC: H03K3/037 ,  H03K3/012

Abstract: In described examples, a latch includes circuitry for latching input information. The circuitry can be precharged in response to an indication of a first mode and can latch the input information to an indication of a second mode. The latch can optionally further latch the input information in response to a node for storing the latched input information.

公开(公告)号：US10734978B2

公开(公告)日：2020-08-04

申请号：US16236330

申请日：2018-12-28

Applicant: Texas Instruments Incorporated

Inventor： Soman Purushothaman ,  Sankar Prasad Debnath ,  Per Torstein Roine ,  Steven C. Bartling ,  Keshav Bhaktavatson Chintamani

IPC: H03K3/037 ,  H03K3/012

Abstract: In described examples, a latch includes circuitry for latching input information. The circuitry can be precharged in response to an indication of a first mode and can latch the input information to an indication of a second mode. The latch can optionally further latch the input information in response to a node for storing the latched input information.

公开(公告)号：US20180248541A1

公开(公告)日：2018-08-30

申请号：US15715290

申请日：2017-09-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Soman Purushothaman ,  Keshav Bhaktavatson Chintamani

IPC: H03K3/037 ,  H03K19/173 ,  H03K19/003 ,  H03K3/012

CPC classification number: H03K3/0375 ,  H03K3/0372 ,  H03K3/356008 ,  H03K3/35625

Abstract: This invention is a retention circuit retaining the state of a circuit node driven by a primary drive circuit. This circuit includes cross coupled first and second inverters and a transmission gate. The transmission gate receives a retention mode signal and isolates the retention circuit and the circuit node when a retention mode is active and connects the retention circuit and the circuit node when the retention mode is inactive. In the preferred embodiment the primary drive circuit is constructed of transistors having a standard voltage threshold and the retention circuit is constructed of transistors having a high voltage threshold greater than said standard voltage threshold. A tristate inverter isolates the retention circuit from the circuit node when not in retention mode and supplies an inverse of a signal from output of said first inverter when in retention mode.

公开(公告)号：US09496024B1

公开(公告)日：2016-11-15

申请号：US14974945

申请日：2015-12-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srinivasa Raghavan Sridhara ,  Sanjeev Kumar Suman ,  Premkumar Seetharaman ,  Keshav Bhaktavatson Chintamani ,  Atul Ramakant Lele ,  Raviprakash S. Rao ,  Parvinder Kumar Rana ,  Ajith Subramonia ,  Vipul K. Singhal ,  Malav Shrikant Shah ,  Bharath Kumar Poluri

IPC: G11C5/14 ,  G11C11/417

CPC classification number: G11C11/417 ,  G11C11/413

Abstract: A system on a chip (SOC) includes a processor and a memory system coupled to the processor. The memory system includes a static random access memory (SRAM) bank and a memory controller. The SRAM bank includes a first switch coupled to a SRAM array power supply and a source of a transistor of an SRAM storage cell in an SRAM array. The SRAM bank also includes a second switch coupled to a NWELL power supply and a bulk of the transistor of the SRAM storage cell. The second switch is configured to close prior to the first switch closing during power up of the SRAM array.

Abstract translation: 芯片上的系统（SOC）包括处理器和耦合到处理器的存储器系统。 存储器系统包括静态随机存取存储器（SRAM）存储体和存储器控制器。 SRAM库包括耦合到SRAM阵列电源的第一开关和SRAM阵列中的SRAM存储单元的晶体管的源极。 SRAM库还包括耦合到NWELL电源和SRAM存储单元的大部分晶体管的第二开关。 第二开关被配置为在SRAM阵列上电期间在第一开关闭合之前关闭。