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    High performance low retention mode leakage flip-flop
    1.
    发明授权
    High performance low retention mode leakage flip-flop 有权

    公开(公告)号：US10340899B2

    公开(公告)日：2019-07-02

    申请号：US15715290

    申请日：2017-09-26

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Soman Purushothaman ,  Keshav Bhaktavatson Chintamani

    IPC: H03K3/037 ,  H03K3/356 ,  H03K3/3562

    Abstract: This invention is a retention circuit retaining the state of a circuit node driven by a primary drive circuit. This circuit includes cross coupled first and second inverters and a transmission gate. The transmission gate receives a retention mode signal and isolates the retention circuit and the circuit node when a retention mode is active and connects the retention circuit and the circuit node when the retention mode is inactive. In the preferred embodiment the primary drive circuit is constructed of transistors having a standard voltage threshold and the retention circuit is constructed of transistors having a high voltage threshold greater than said standard voltage threshold. A tristate inverter isolates the retention circuit from the circuit node when not in retention mode and supplies an inverse of a signal from output of said first inverter when in retention mode.

    SINGLE SUPPLY LEVEL SHIFTER WITH IMPROVED RISE TIME AND REDUCED LEAKAGE
    2.
    发明申请
    SINGLE SUPPLY LEVEL SHIFTER WITH IMPROVED RISE TIME AND REDUCED LEAKAGE 有权
    单电源水平改善，提高了上升时间，减少了泄漏

    公开(公告)号：US20150244372A1

    公开(公告)日：2015-08-27

    申请号：US14186849

    申请日：2014-02-21

    Applicant: Texas Instruments Incorporated

    Inventor： Soman Purushothaman

    IPC: H03K19/0185

    CPC classification number: H03K19/018521 ,  H03K19/0013 ,  H03K19/00384

    Abstract: A single supply level shifter converts an input logic level signal IN into level shifted OUT and OUT_X. An IN inverter generates OUT at an OUT Node. The IN inverter is coupled at an INT node to a VDD supply rail, through an INT_Node PFET that controls the INT Node based on OUT_X. An OUT_X network includes a separate IN_X inverter (generating inverted IN independent of level shifting), and an OUT_X circuit that controls pull-up/down of an OUT_X Node to generate OUT_X. The OUT_X circuit receives control inputs from both IN and IN_X inverters, and controls pull-up/down at the OUT_X Node. The OUT_X circuit is configured as a three FET stack: a pull-up/down PFET/NFET pair receives IN_X (inverted IN), and an OUT_X Node control PFET, coupled between the pull-up PFET and the OUT_X Node, receives OUT (inverted IN). Based on OUT and IN_X, the OUT_X circuit generates OUT_X as an inverted OUT (including supplying OUT_X to the INT_Node PFET to control the INT Node (including OUT pull-up).

    Abstract translation: 单个电源电平移位器将输入逻辑电平信号IN转换为电平移位OUT和OUT_X。 IN逆变器在OUT节点处产生OUT。 IN反相器通过INT_Node PFET将INT节点耦合到VDD电源轨，该INT_Node PFET基于OUT_X控制INT节点。 OUT_X网络包括一个单独的IN_X反相器（独立于电平转换产生反相的IN），以及一个OUT_X电路，用于控制OUT_X节点的上拉/下拉以产生OUT_X。 OUT_X电路从IN和IN_X反相器接收控制输入，并控制OUT_X节点的上拉/下拉。 OUT_X电路配置为三个FET堆叠：上拉/下拉PFET / NFET对接收IN_X（反相IN），并且耦合在上拉PFET和OUT_X节点之间的OUT_X节点控制PFET接收OUT（ 倒置IN）。 基于OUT和IN_X，OUT_X电路产生OUT_X作为反相OUT（包括向INT_Node PFET提供OUT_X以控制INT节点（包括OUT上拉）。

    Single supply level shifter with improved rise time and reduced leakage
    4.
    发明授权
    Single supply level shifter with improved rise time and reduced leakage 有权
    单电源电平转换器具有改善的上升时间和减少泄漏

    公开(公告)号：US09225333B2

    公开(公告)日：2015-12-29

    申请号：US14186849

    申请日：2014-02-21

    Applicant: Texas Instruments Incorporated

    Inventor： Soman Purushothaman

    IPC: H03K19/0175 ,  H03K19/0185 ,  H03K19/00 ,  H03K19/003

    CPC classification number: H03K19/018521 ,  H03K19/0013 ,  H03K19/00384

    Abstract: A single supply level shifter converts an input logic level IN into level shifted OUT and OUT_X. An IN inverter generates level-shifted OUT at an OUT Node. IN is coupled at an INT Node to a VDD supply rail, through an INT_Node PFET that controls the INT Node based on OUT_X. An OUT_X network includes a separate IN_X inverter (generating inverted IN independent of level shifting), and an OUT_X circuit that controls pull-up/down of an OUT_X Node to generate level-shifted OUT_X, receiving control inputs from both IN and IN_X inverters. The OUT_X circuit is a three FET stack: a pull-up/down PFET/NFET pair receives IN_X, and an OUT_X Node control PFET, coupled between the pull-up PFET and the OUT_X Node, receives OUT. Based on OUT and IN_X, the OUT_X circuit generates OUT_X as an inverted OUT (including supplying OUT_X to the INT_Node PFET to control the INT Node (including OUT pull-up).

    Abstract translation: 单个电源电平移位器将输入逻辑电平IN转换为电平移位OUT和OUT_X。 IN逆变器在OUT节点处产生电平移位的OUT。 IN通过INT_Node PFET将INT节点耦合到VDD电源轨，该INT_Node PFET基于OUT_X控制INT节点。 OUT_X网络包括一个独立的IN_X反相器（独立于电平转换产生反相的IN），以及一个OUT_X电路，用于控制OUT_X节点的上拉/下拉以产生电平移位的OUT_X，从IN和IN_X反相器接收控制输入。 OUT_X电路是三个FET堆叠：上拉/下拉PFET / NFET对接收IN_X，并且耦合在上拉PFET和OUT_X节点之间的OUT_X节点控制PFET接收OUT。 基于OUT和IN_X，OUT_X电路产生OUT_X作为反相OUT（包括向INT_Node PFET提供OUT_X以控制INT节点（包括OUT上拉）。

    Low area enable flip-flop
    6.
    发明授权
    Low area enable flip-flop 有权

    公开(公告)号：US10541680B2

    公开(公告)日：2020-01-21

    申请号：US14585263

    申请日：2014-12-30

    Applicant: Texas Instruments Incorporated

    Inventor： Subhankar Das ,  Soman Purushothaman

    IPC: H03K3/289 ,  H03K3/3562 ,  H03K3/037

    Abstract: The disclosure provides a flip-flop. The flip-flop includes a master latch. The master latch receives a flip-flop input, a clock input, an inverted clock input, an enable signal and an inverted enable signal. A slave latch is coupled to the master latch and receives the enable signal and the inverted enable signal. An output inverter is coupled to the slave latch and generates a flip-flop output.

    HIGH PERFORMANCE LOW RETENTION MODE LEAKAGE FLIP-FLOP
    7.
    发明申请
    HIGH PERFORMANCE LOW RETENTION MODE LEAKAGE FLIP-FLOP 审中-公开

    公开(公告)号：US20180248541A1

    公开(公告)日：2018-08-30

    申请号：US15715290

    申请日：2017-09-26

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Soman Purushothaman ,  Keshav Bhaktavatson Chintamani

    IPC: H03K3/037 ,  H03K19/173 ,  H03K19/003 ,  H03K3/012

    CPC classification number: H03K3/0375 ,  H03K3/0372 ,  H03K3/356008 ,  H03K3/35625

    Abstract: This invention is a retention circuit retaining the state of a circuit node driven by a primary drive circuit. This circuit includes cross coupled first and second inverters and a transmission gate. The transmission gate receives a retention mode signal and isolates the retention circuit and the circuit node when a retention mode is active and connects the retention circuit and the circuit node when the retention mode is inactive. In the preferred embodiment the primary drive circuit is constructed of transistors having a standard voltage threshold and the retention circuit is constructed of transistors having a high voltage threshold greater than said standard voltage threshold. A tristate inverter isolates the retention circuit from the circuit node when not in retention mode and supplies an inverse of a signal from output of said first inverter when in retention mode.

    LOW AREA ENABLE FLIP-FLOP
    8.
    发明申请
    LOW AREA ENABLE FLIP-FLOP 审中-公开
    低区域使用FLIP-FLOP

    公开(公告)号：US20160191028A1

    公开(公告)日：2016-06-30

    申请号：US14585263

    申请日：2014-12-30

    Applicant: Texas Instruments Incorporated

    Inventor： Subhankar Das ,  Soman Purushothaman

    IPC: H03K3/3562

    Abstract: The disclosure provides a flip-flop. The flip-flop includes a master latch. The master latch receives a flip-flop input, a clock input, an inverted clock input, an enable signal and an inverted enable signal. A slave latch is coupled to the master latch and receives the enable signal and the inverted enable signal. An output inverter is coupled to the slave latch and generates a flip-flop output.

    Abstract translation: 本公开提供了一种触发器。 触发器包括主锁存器。 主锁存器接收触发器输入，时钟输入，反相时钟输入，使能信号和反相使能信号。 从锁存器耦合到主锁存器并且接收使能信号和反相使能信号。 输出反相器耦合到从锁存器并产生触发器输出。

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