公开(公告)号：US20150074306A1

公开(公告)日：2015-03-12

申请号：US14482474

申请日：2014-09-10

Applicant: Texas Instruments Incorporated

Inventor： Ravishankar S. Ayyagari ,  Supreet Joshi ,  Bharath Patil ,  Madhav Tejaswi Boddhapu

IPC: G06F13/362 ,  G06F13/38

CPC classification number: G06F13/4295 ,  G06F13/4072

Abstract: In a single wire communications interface embodiment, a single wire is coupled between a master device and at least one slave device, the master device configured for transmitting data words as serial data to and for receiving data words as serial data from the at least one slave device, and the at least one slave device configured for transmitting data words as serial data to and receiving data words as serial data from the master device; wherein prior to transmission of any data word on the single wire by one of the master device and the slave device, a sync pulse is first transmitted on the single wire. Integrated circuit embodiments for implementing the single wire communications interface, and method embodiments incorporating the single wire communications interface are disclosed. Additional embodiments are disclosed.

Abstract translation: 在单线通信接口实施例中，单线耦合在主设备和至少一个从设备之间，主设备被配置为将数据字作为串行数据发送到串行数据，并将数据字作为来自至少一个从站的串行数据接收 所述至少一个从设备被配置为将来自所述主设备的数据字作为串行数据发送到数据字并作为串行数据接收; 其中在通过主设备和从设备之一在单线上发送任何数据字之前，首先在单线上发送同步脉冲。 公开了用于实现单线通信接口的集成电路实施例以及并入单线通信接口的方法实施例。 公开了另外的实施例。

公开(公告)号：US10108578B2

公开(公告)日：2018-10-23

申请号：US14482474

申请日：2014-09-10

Applicant: Texas Instruments Incorporated

Inventor： Ravishankar S. Ayyagari ,  Supreet Joshi ,  Bharath Patil ,  Madhav Tejaswi Boddhapu

IPC: G06F13/00 ,  G06F13/42 ,  G06F13/40

Abstract: In a single wire communications interface embodiment, a single wire is coupled between a master device and at least one slave device, the master device configured for transmitting data words as serial data to and for receiving data words as serial data from the at least one slave device, and the at least one slave device configured for transmitting data words as serial data to and receiving data words as serial data from the master device; wherein prior to transmission of any data word on the single wire by one of the master device and the slave device, a sync pulse is first transmitted on the single wire. Integrated circuit embodiments for implementing the single wire communications interface, and method embodiments incorporating the single wire communications interface are disclosed. Additional embodiments are disclosed.

公开(公告)号：US09548752B1

公开(公告)日：2017-01-17

申请号：US15048027

申请日：2016-02-19

Applicant: Texas Instruments Incorporated

Inventor： Neeraj Shrivastava ,  Supreet Joshi ,  Himanshu Varshney ,  Jafar Sadique Kaviladath ,  Visvesvaraya Pentakota ,  Shagun Dusad

IPC: H03M1/66 ,  H03M1/10 ,  H03M1/78 ,  H03M1/74

CPC classification number: H03M1/1009 ,  H03M1/1019 ,  H03M1/1057 ,  H03M1/66 ,  H03M1/742 ,  H03M1/745 ,  H03M1/785

Abstract: The disclosure provides a current steering digital to analog converter (DAC) that includes a plurality of DAC elements. At least one DAC element of the plurality of DAC elements is coupled to a calibration circuit. The calibration circuit includes a fixed current source coupled to a primary node of the DAC element through a first estimation switch. A digital code generator is coupled to the primary node, and generates a first digital code corresponding to a primary voltage generated at the primary node. The digital code generator generates a second digital code. A correction DAC is coupled to the digital code generator and generates a bias voltage based on the second digital code. The bias voltage is provided to the DAC element such that a current flowing through each DAC element of the plurality of DAC elements is equal.

Abstract translation: 本公开提供了包括多个DAC元件的电流转向数模转换器（DAC）。 多个DAC元件中的至少一个DAC元件耦合到校准电路。 校准电路包括通过第一估计开关耦合到DAC元件的主节点的固定电流源。 数字码发生器耦合到主节点，并且产生对应于在主节点处产生的主电压的第一数字码。 数字代码生成器产生第二数字代码。 校正DAC耦合到数字代码发生器并且基于第二数字代码产生偏置电压。 偏置电压被提供给DAC元件，使得流过多个DAC元件中的每个DAC元件的电流相等。