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    Area efficient parallel test data path for embedded memories
    2.
    发明授权
    Area efficient parallel test data path for embedded memories 有权

    公开(公告)号：US10460821B2

    公开(公告)日：2019-10-29

    申请号：US15896817

    申请日：2018-02-14

    Applicant: Texas Instruments Incorporated

    Inventor： Prakash Narayanan ,  Nikita Naresh ,  Vaskar Sarkar ,  Rajat Mehrotra

    IPC: G11C29/12 ,  G11C29/38 ,  G11C29/40 ,  G11C29/04 ,  G11C29/26

    Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.

    AREA EFFICIENT PARALLEL TEST DATA PATH FOR EMBEDED MEMORIES
    3.
    发明申请
    AREA EFFICIENT PARALLEL TEST DATA PATH FOR EMBEDED MEMORIES 审中-公开

    公开(公告)号：US20170157524A1

    公开(公告)日：2017-06-08

    申请号：US15434717

    申请日：2017-02-16

    Applicant: Texas Instruments Incorporated

    Inventor： Prakash Narayanan ,  Nikita Naresh ,  Vaskar Sarkar ,  Rajat Mehrotra

    IPC: G11C29/00

    CPC classification number: G11C29/12 ,  G11C29/38 ,  G11C29/40 ,  G11C2029/0401 ,  G11C2029/2602

    Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.

    AREA-EFFICIENT PARALLEL TEST DATA PATH FOR EMBEDDED MEMORIES
    5.
    发明申请
    AREA-EFFICIENT PARALLEL TEST DATA PATH FOR EMBEDDED MEMORIES 审中-公开

    公开(公告)号：US20170125125A1

    公开(公告)日：2017-05-04

    申请号：US15066924

    申请日：2016-03-10

    Applicant: Texas Instruments Incorporated

    Inventor： Prakash Narayanan ,  Nikita Naresh ,  Vaskar Sarkar ,  Rajat Mehrotra

    IPC: G11C29/12

    CPC classification number: G11C29/12 ,  G11C29/38 ,  G11C29/40 ,  G11C2029/0401 ,  G11C2029/2602

    Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit of the system-on-a-chip (SoC) type. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.

    AREA EFFICIENT PARALLEL TEST DATA PATH FOR EMBEDDED MEMORIES
    7.
    发明申请
    AREA EFFICIENT PARALLEL TEST DATA PATH FOR EMBEDDED MEMORIES 审中-公开

    公开(公告)号：US20180174663A1

    公开(公告)日：2018-06-21

    申请号：US15896817

    申请日：2018-02-14

    Applicant: Texas Instruments Incorporated

    Inventor： Prakash Narayanan ,  Nikita Naresh ,  Vaskar Sarkar ,  Rajat Mehrotra

    IPC: G11C29/12

    CPC classification number: G11C29/12 ,  G11C29/38 ,  G11C29/40 ,  G11C2029/0401 ,  G11C2029/2602

    Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.

    Area efficient parallel test data path for embedded memories
    8.
    发明授权
    Area efficient parallel test data path for embedded memories 有权

    公开(公告)号：US09899103B2

    公开(公告)日：2018-02-20

    申请号：US15434717

    申请日：2017-02-16

    Applicant: Texas Instruments Incorporated

    Inventor： Prakash Narayanan ,  Nikita Naresh ,  Vaskar Sarkar ,  Rajat Mehrotra

    IPC: G11C7/00 ,  G11C29/12

    CPC classification number: G11C29/12 ,  G11C29/38 ,  G11C29/40 ,  G11C2029/0401 ,  G11C2029/2602

    Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.

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