公开(公告)号：US20180174663A1

公开(公告)日：2018-06-21

申请号：US15896817

申请日：2018-02-14

申请人： Texas Instruments Incorporated

发明人： Prakash Narayanan ,  Nikita Naresh ,  Vaskar Sarkar ,  Rajat Mehrotra

IPC分类号： G11C29/12

CPC分类号： G11C29/12 ,  G11C29/38 ,  G11C29/40 ,  G11C2029/0401 ,  G11C2029/2602

摘要： A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.

公开(公告)号：US09911467B2

公开(公告)日：2018-03-06

申请号：US15275732

申请日：2016-09-26

申请人： SK hynix Inc.

发明人： Jun Ho Cheon

IPC分类号： G11C7/10

CPC分类号： G11C7/1006 ,  G11C7/1045 ,  G11C13/00 ,  G11C29/12005 ,  G11C2013/0088 ,  G11C2029/1202 ,  G11C2029/2602

摘要： A resistance variable memory apparatus may include a memory cell array and a controller. The memory cell array may include a plurality of resistance variable memory cells. The controller may control a current path flowing through any one memory cell and a current path flowing through the other memory cell to be formed differently from each other in response to at least two address signals.

公开(公告)号：US09899103B2

公开(公告)日：2018-02-20

申请号：US15434717

申请日：2017-02-16

申请人： Texas Instruments Incorporated

发明人： Prakash Narayanan ,  Nikita Naresh ,  Vaskar Sarkar ,  Rajat Mehrotra

IPC分类号： G11C7/00 ,  G11C29/12

CPC分类号： G11C29/12 ,  G11C29/38 ,  G11C29/40 ,  G11C2029/0401 ,  G11C2029/2602

摘要： A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.

公开(公告)号：US20170336989A1

公开(公告)日：2017-11-23

申请号：US15669538

申请日：2017-08-04

申请人： Micron Technology, Inc.

发明人： Jason T. Zawodny ,  Glen E. Hush ,  Troy A. Manning ,  Timothy P. Finkbeiner

IPC分类号： G06F3/06 ,  G11C8/12 ,  G11C7/10 ,  G11C29/28 ,  G11C29/26

CPC分类号： G06F3/0611 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0683 ,  G06F15/7821 ,  G11C5/025 ,  G11C7/10 ,  G11C7/1006 ,  G11C8/12 ,  G11C29/28 ,  G11C2029/2602

摘要： The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.

公开(公告)号：US09679665B2

公开(公告)日：2017-06-13

申请号：US14527352

申请日：2014-10-29

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Martin Eckert ,  Otto A. Torreiter ,  Christian Zoellin

IPC分类号： G11C29/12 ,  G01R31/3187 ,  G06F11/22 ,  G06F11/27 ,  G11C29/26 ,  G06F1/32 ,  G11C29/32 ,  G01R31/28 ,  G11C29/50 ,  G01R31/30 ,  G06F11/10 ,  G11C29/04 ,  G11C29/36 ,  G01R31/317

CPC分类号： G11C29/12015 ,  G01R31/2856 ,  G01R31/3004 ,  G01R31/31701 ,  G01R31/31721 ,  G01R31/3187 ,  G06F1/3275 ,  G06F1/3287 ,  G06F11/1068 ,  G06F11/2236 ,  G06F11/27 ,  G11C29/26 ,  G11C29/50 ,  G11C2029/0401 ,  G11C2029/2602 ,  G11C2029/3202 ,  G11C2029/3602

摘要： A method including determining a test duration for testing each of a plurality of memory arrays individually coupled to a plurality of array built-in-self test (ABIST) engines, the test duration is equal to a time period required by each of the plurality of ABIST engines to test each of the plurality of memory arrays, determining a corresponding delay value for each of the plurality of ABIST engines, each of the corresponding delay values is based on the test duration for each of the plurality of memory arrays, and consecutively delaying the start of processing of each of the plurality of ABIST engines by providing each of the corresponding delay values to each of a plurality of programmable delay units individually coupled to each of the plurality of ABIST engines, the start of processing of each of the plurality of ABIST engines is delayed by a different corresponding delay value.

公开(公告)号：US20170062074A1

公开(公告)日：2017-03-02

申请号：US15176618

申请日：2016-06-08

申请人： Samsung Electronics Co., Ltd.

发明人： Dong-Wook KIM ,  Jae-Hong KIM ,  Jun-Ki JEONG

IPC分类号： G11C29/08 ,  G11C8/10 ,  G11C7/10

CPC分类号： G11C29/56008 ,  G11C29/26 ,  G11C2029/1802 ,  G11C2029/2602 ,  G11C2029/5604

摘要： A memory test system may include a tester and N memory devices, where N is a positive integer greater than 1. The tester may generate test signals. A K-th memory device of the N memory devices includes a plurality of K-th memory banks and a K-th decoder, where K is each positive integer equal to or smaller than N. The K-th memory banks may be configured to operate based on first internal signals and each of the K-th memory banks includes a plurality of unit blocks. The K-th decoder may be configured to convert the test signals corresponding to the first test to the first internal signals based on a K-th conversion relation and update the K-th conversion relation based on a result of the first test with respect to the K-th memory device.

摘要翻译： 存储器测试系统可以包括测试器和N个存储器件，其中N是大于1的正整数。测试器可以产生测试信号。 N个存储器件的第K个存储器件包括多个第K个存储器组和第K个解码器，其中K个等于或小于N的正整数。第K个存储器组可以被配置为 基于第一内部信号进行操作，并且每个第K个存储体包括多个单位块。 第K解码器可以被配置为基于第K个转换关系将对应于第一测试的测试信号转换为第一内部信号，并且基于第一测试的结果来更新第K个转换关系 第K个存储器件。

公开(公告)号：US09583216B2

公开(公告)日：2017-02-28

申请号：US14656966

申请日：2015-03-13

申请人： ANALOG DEVICES, INC.

发明人： Eric C. Jones ,  Andrew J. Allan

IPC分类号： G11C29/42 ,  G11C29/36

CPC分类号： G11C29/42 ,  G11C29/1201 ,  G11C29/36 ,  G11C2029/2602

摘要： A system implementing an MBIST device is disclosed. The system includes an ECC-protected memory and the MBIST device for self-test of the memory. The MBIST device includes a first access port communicatively connected to the memory via a first path, the first path excluding the ECC logic associated with the embedded memory, and a second access port communicatively connected to the memory via a second path, the second path including the ECC logic associated with the memory. The device is configured to test the memory, in a first mode of operation, via the first path and, in a second mode of operation, via the second path. One advantage of such system includes re-using, with little additional die area, of MBIST logic already required for manufacturing test of the product (first mode of operation) for system or application level tests that may be carried out by customers (second mode of operation).

摘要翻译： 公开了一种实现MBIST设备的系统。 该系统包括ECC保护的存储器和用于存储器自检的MBIST设备。 MBIST设备包括经由第一路径通信地连接到存储器的第一访问端口，排除与嵌入式存储器相关联的ECC逻辑的第一路径，以及经由第二路径通信地连接到存储器的第二访问端口，第二路径包括 与存储器相关联的ECC逻辑。 该设备被配置为经由第一路径以第一操作模式经由第二路径在第二操作模式下测试存储器。 这种系统的一个优点包括对于可由客户执行的系统或应用程序级测试（第二模式）对产品的制造测试（第一操作模式）已经需要的MBIST逻辑重新使用少量额外的管芯面积 操作）。

公开(公告)号：US20160350196A1

公开(公告)日：2016-12-01

申请号：US15150474

申请日：2016-05-10

申请人： FUJITSU LIMITED

发明人： Makoto SUGA ,  AKIO TOKOYODA ,  Masatoshi Aihara ,  Koji HOSOE ,  KOICHIRO TAKAYAMA

IPC分类号： G06F11/273

CPC分类号： G06F11/00 ,  G06F2201/805 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/36 ,  G11C29/44 ,  G11C29/46 ,  G11C2029/2602 ,  G11C2029/3602 ,  G11C2029/4402 ,  G11C2029/5604

摘要： The arithmetic processing device includes a first memory control unit configured to control an access to a first memory, a second memory control unit configured to control an access to a second memory. The arithmetic processing device further includes a diagnostic control unit configured to sequentially diagnose parts within the first memory via the first memory control unit, and configured to sequentially store in the second memory via the second memory control unit, diagnostic results of sequentially diagnosing the parts in parallel with the diagnosing the parts via the first memory control unit.

摘要翻译： 算术处理装置包括被配置为控制对第一存储器的访问的第一存储器控制单元，被配置为控制对第二存储器的访问的第二存储器控制单元。 所述算术处理装置还包括：诊断控制部，被配置为经由所述第一存储器控制部对所述第一存储器内的各部分顺序进行诊断，并且经由所述第二存储器控制部顺序地存储在所述第二存储器中， 与通过第一存储器控制单元诊断部件并行。

公开(公告)号：US20160268007A1

公开(公告)日：2016-09-15

申请号：US14656966

申请日：2015-03-13

申请人： ANALOG DEVICES, INC.

发明人： Eric C. Jones ,  ANDREW J. ALLAN

IPC分类号： G11C29/42 ,  G11C29/36

CPC分类号： G11C29/42 ,  G11C29/1201 ,  G11C29/36 ,  G11C2029/2602

摘要： A system implementing an MBIST device is disclosed. The system includes an ECC-protected memory and the MBIST device for self-test of the memory. The MBIST device includes a first access port communicatively connected to the memory via a first path, the first path excluding the ECC logic associated with the embedded memory, and a second access port communicatively connected to the memory via a second path, the second path including the ECC logic associated with the memory. The device is configured to test the memory, in a first mode of operation, via the first path and, in a second mode of operation, via the second path. One advantage of such system includes re-using, with little additional die area, of MBIST logic already required for manufacturing test of the product (first mode of operation) for system or application level tests that may be carried out by customers (second mode of operation).

摘要翻译： 公开了一种实现MBIST设备的系统。 该系统包括ECC保护的存储器和用于存储器自检的MBIST设备。 MBIST设备包括经由第一路径通信地连接到存储器的第一访问端口，排除与嵌入式存储器相关联的ECC逻辑的第一路径，以及经由第二路径通信地连接到存储器的第二访问端口，第二路径包括 与存储器相关联的ECC逻辑。 该设备被配置为经由第一路径以第一操作模式经由第二路径在第二操作模式下测试存储器。 这种系统的一个优点包括对于可由客户执行的系统或应用程序级测试（第二模式）对产品的制造测试（第一操作模式）已经需要的MBIST逻辑重新使用少量额外的管芯面积 操作）。

公开(公告)号：US20160141052A1

公开(公告)日：2016-05-19

申请号：US14930785

申请日：2015-11-03

申请人： EM Microelectronic-Marin SA

发明人： Lubomir PLAVEC ,  Filippo MARINELLI ,  Miloslav KUBAR

IPC分类号： G11C29/08 ,  G11C7/12 ,  G11C7/22 ,  G11C8/10

CPC分类号： G11C29/08 ,  G11C7/12 ,  G11C7/22 ,  G11C8/10 ,  G11C29/18 ,  G11C29/34 ,  G11C2029/1202 ,  G11C2029/2602

摘要： The electronic memory device comprises a non-volatile memory matrix organized in rows and columns, an address decoder with address input lines for selecting a row according to a particular address given on the address input lines. Additional address mask input lines are provided, each address mask input line being assigned to an address input line, wherein an address mask input line in activated state has the effect of ignoring the assigned address input line. The method for testing said electronic memory device is performed with a significant lower number of read/write operations, since by ignoring a particular address line a plurality of write operations can be performed simultaneously.

摘要翻译： 电子存储装置包括以行和列组织的非易失性存储器矩阵，地址解码器，其具有地址输入线，用于根据地址输入线上给出的特定地址来选择行。 提供附加地址掩码输入线，每个地址掩码输入线被分配给地址输入线，其中激活状态下的地址掩码输入线具有忽略分配的地址输入线的效果。 由于通过忽略特定的地址线，可以同时执行多个写入操作，所以测试所述电子存储器件的方法以显着较低数量的读/写操作执行。