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公开(公告)号：US5027270A
公开(公告)日：1991-06-25
申请号：US255791
申请日：1988-10-11
CPC分类号： G06F9/3814 , G06F12/0859 , G06F9/3802
摘要： A processor controlled interface between a processor, instruction cache, and main memory provides for simultaneously refilling the cache with an instruction block from main memory and processing the instructions in the block while they are being written to the cache.
摘要翻译： 处理器，指令高速缓存和主存储器之间的处理器控制的接口提供用于从主存储器中的指令块同时重新填充高速缓存并且在块被写入高速缓存时处理该块中的指令。
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2.发明授权Processor chip having on-chip circuitry for generating a programmable external clock signal and for controlling data patterns 失效具有用于产生可编程外部时钟信号并用于控制数据模式的片上电路的处理器芯片
公开(公告)号：US5734877A
公开(公告)日：1998-03-31
申请号：US715246
申请日：1996-09-19
CPC分类号： G06F1/08
摘要： Techniques for matching the speed of a microprocessor to potentially slower external system components. A master clock signal is communicated to a clock generator on the processor chip. The clock generator provides at least one external clock signal, which is communicated to various portions of the system. The clock generator includes programmable clock division circuitry that allows the external clock signal to be generated at any selected one of a plurality of fractions of the master clock frequency. The data pattern (the particular cycles in a sequence during which the processor outputs a data word as part of a multiple-data-word sequence) is programmable independently of the external clock programming.
摘要翻译： 将微处理器速度与潜在较慢的外部系统组件相匹配的技术。 主时钟信号被传送到处理器芯片上的时钟发生器。 时钟发生器提供至少一个外部时钟信号，其被传送到系统的各个部分。 时钟发生器包括可编程时钟分频电路，其允许外部时钟信号以主时钟频率的多个分数中的任何选定的一个产生。 数据模式（处理器输出数据字作为多数据字序列的一部分的序列中的特定周期）可独立于外部时钟编程而编程。
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3.发明授权Processor chip for using an external clock to generate an internal clock and for using data transmit patterns in combination with the internal clock to control transmission of data words to an external memory 失效处理器芯片，用于使用外部时钟来产生内部时钟，并使用与内部时钟相结合的数据传输模式来控制数据字传输到外部存储器
公开(公告)号：US5978926A
公开(公告)日：1999-11-02
申请号：US36684
申请日：1998-03-09
IPC分类号： G06F1/08
CPC分类号： G06F1/08
摘要： Techniques for matching the speed of a microprocessor to potentially slower external system components. A master clock signal is communicated to a clock generator on the processor chip. The clock generator provides at least one external clock signal, which is communicated to various portions of the system. The clock generator includes programmable clock division circuitry that allows the external clock signal to be generated at any selected one of a plurality of fractions of the master clock frequency. The data pattern (the particular cycles in a sequence during which the processor outputs a data word as part of a multiple-data-word sequence) is programmable independently of the external clock programming.
摘要翻译： 将微处理器速度与潜在较慢的外部系统组件相匹配的技术。 主时钟信号被传送到处理器芯片上的时钟发生器。 时钟发生器提供至少一个外部时钟信号，其被传送到系统的各个部分。 时钟发生器包括可编程时钟分频电路，其允许外部时钟信号以主时钟频率的多个分数中的任何选定的一个产生。 数据模式（处理器输出数据字作为多数据字序列的一部分的序列中的特定周期）可独立于外部时钟编程而编程。
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公开(公告)号：US06856622B1
公开(公告)日：2005-02-15
申请号：US09789879
申请日：2001-02-20
CPC分类号： H04L49/508 , H04L12/18 , H04L49/101 , H04L49/201 , H04L49/254
摘要： A method of facilitating the scheduling of a first multicast request signal of a series of multicast request signals is disclosed, wherein the first request signal is generated to enable the transmission of a multicast data cell by a source port processor to at least one destination port processor. In a preferred embodiment of the invention, the first request signal is received by a roster storage chip associated with a scheduler subsystem. The first request signal has associated therewith a multicast label of a first value and is adapted to schedule transmission of the first multicast cell to the at least one destination port processor at a first time. A roster of the at least one destination port processor to which the first multicast cell is destined is then generated. A dependence distance associated with the first request signal is determined. The dependence distance comprises the numerical value of the difference between a current multicast cell number (CMCN) and a previous multicast cell number (PMCN). The roster and the dependence distance are transmitted to one of the at least one scheduler chips, such transmission causing the roster and the dependence distance to occupy a second tail entry slot of a second circular buffer associated with the one of the at least one scheduler chips. The second tail entry slot has associated therewith a first multicast table index (MTI) comprising a numerical value. The scheduler chip further has associated therewith a head entry slot having associated therewith a second MTI comprising a numerical value. A first numerical parameter comprising the numerical sum of the dependence distance and the first MTI is determined. If the first numerical parameter is higher in value than the second MTI, the first request signal is arbitrated.
摘要翻译： 公开了一种便于对一系列多播请求信号的第一多播请求信号进行调度的方法，其中生成第一请求信号，以使能源端口处理器将多播数据信元传输到至少一个目的端口处理器 。 在本发明的优选实施例中，第一请求信号由与调度器子系统相关联的名单存储芯片接收。 第一请求信号已经与第一个值相关联的多播标签，并且适于在第一时间将该第一多播小区的传输调度到该至少一个目的地端口处理器。 然后生成第一多播小区所指定的至少一个目的地端口处理器的名单。 确定与第一请求信号相关联的依赖距离。 依赖距离包括当前多播小区号（CMCN）和之前的多播小区号（PMCN）之间的差值的数值。 该名单和依赖距离被发送到至少一个调度器芯片中的一个，这样的传输导致花名册和依赖距离占据与至少一个调度器码片之一相关联的第二循环缓冲器的第二尾部入口时隙 。 第二尾部进入时隙具有与其相关联的包括数值的第一多播表索引（MTI）。 调度器芯片还具有与其相关联的头入口槽，其具有包括数值的第二MTI。 确定包括依赖距离和第一MTI的数字和的第一数值参数。 如果第一数值参数的值高于第二MTI，则对第一请求信号进行仲裁。
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公开(公告)号：US4972338A
公开(公告)日：1990-11-20
申请号：US185325
申请日：1988-04-19
申请人： John H. Crawford , Paul S. Ries
发明人： John H. Crawford , Paul S. Ries
CPC分类号： G06F12/1027 , G06F12/145
摘要： Microprocessor architecture for an address translation unit which provides two levels of cache memory management is described. Segmentation registers and an associated segmentation table in main memory provide a first level of memory management which includes attribute bits used for protection, priority, etc. A second page cache memory and an associated page directory and page table in main memory provide a second level of management with independent protection on a page level. eyboard
摘要翻译： 描述了提供两级高速缓存存储器管理的地址转换单元的微处理器架构。 主存储器中的分段寄存器和相关联的分段表提供第一级存储器管理，其包括用于保护，优先级等的属性位。主存储器中的第二页高速缓冲存储器和相关联的页目录和页表提供第二级 在一个页面上具有独立保护的管理。
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公开(公告)号：US5173872A
公开(公告)日：1992-12-22
申请号：US73054
申请日：1987-07-13
申请人： John H. Crawford , Paul S. Ries
发明人： John H. Crawford , Paul S. Ries
CPC分类号： G06F12/1027 , G06F12/145
摘要： A content addressable memory (CAM) for use with a microprocessor allows comparison of the contents of the memory with input data. The CAM further allows certain bits of input data to be ignored from comparison. This feature allows certain bits, such as a bit indicating whether read or write access is allowed to certain information, to be ignored when the system is, for example, in a supervisory mode. Also disclosed is a method of precharging a hit line, which indicates whether or not a match was found in memory during the comparison, in order to increase the speed of the comparison process.
摘要翻译： 与微处理器一起使用的内容可寻址存储器（CAM）允许将存储器的内容与输入数据进行比较。 CAM进一步允许从比较中忽略输入数据的某些位。 该功能允许在系统例如处于监控模式时忽略诸如指示是否允许读取或写入访问某些信息的某些位。 还公开了一种对比较过程中指示是否在存储器中发现匹配的命中行的预充电方法，以便提高比较处理的速度。
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7.发明授权Virtual memory management method and apparatus utilizing separate and independent segmentation and paging mechanism 失效虚拟内存管理方法和设备利用独立且独立的分段和寻呼机制
公开(公告)号：US5321836A
公开(公告)日：1994-06-14
申请号：US506211
申请日：1990-04-09
申请人： John H. Crawford , Paul S. Ries
发明人： John H. Crawford , Paul S. Ries
CPC分类号： G06F12/1027 , G06F12/145
摘要： Microprocessor architecture for an address translation unit which provides two levels of memory management is described. Segmentation registers and an associated segmentation table in main memory provide a first level of memory management which includes attribute bits used for protection, priority, etc. A page cache memory and an associated page directory and page table in main memory provide a second level of management with independent protection on a page level.
摘要翻译： 描述了提供两级存储器管理的地址转换单元的微处理器架构。 主存储器中的分段寄存器和相关联的分段表提供了第一级存储器管理，其包括用于保护，优先级等的属性位。主存储器中的页面高速缓存存储器和关联的页目录和页表提供第二级管理 具有页面级别的独立保护。
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