-
1.发明授权Processor chip for using an external clock to generate an internal clock and for using data transmit patterns in combination with the internal clock to control transmission of data words to an external memory 失效处理器芯片，用于使用外部时钟来产生内部时钟，并使用与内部时钟相结合的数据传输模式来控制数据字传输到外部存储器
公开(公告)号：US5978926A
公开(公告)日：1999-11-02
申请号：US36684
申请日：1998-03-09
IPC分类号： G06F1/08
CPC分类号： G06F1/08
摘要： Techniques for matching the speed of a microprocessor to potentially slower external system components. A master clock signal is communicated to a clock generator on the processor chip. The clock generator provides at least one external clock signal, which is communicated to various portions of the system. The clock generator includes programmable clock division circuitry that allows the external clock signal to be generated at any selected one of a plurality of fractions of the master clock frequency. The data pattern (the particular cycles in a sequence during which the processor outputs a data word as part of a multiple-data-word sequence) is programmable independently of the external clock programming.
摘要翻译： 将微处理器速度与潜在较慢的外部系统组件相匹配的技术。 主时钟信号被传送到处理器芯片上的时钟发生器。 时钟发生器提供至少一个外部时钟信号，其被传送到系统的各个部分。 时钟发生器包括可编程时钟分频电路，其允许外部时钟信号以主时钟频率的多个分数中的任何选定的一个产生。 数据模式（处理器输出数据字作为多数据字序列的一部分的序列中的特定周期）可独立于外部时钟编程而编程。
-
2.发明授权Processor chip having on-chip circuitry for generating a programmable external clock signal and for controlling data patterns 失效具有用于产生可编程外部时钟信号并用于控制数据模式的片上电路的处理器芯片
公开(公告)号：US5734877A
公开(公告)日：1998-03-31
申请号：US715246
申请日：1996-09-19
CPC分类号： G06F1/08
摘要： Techniques for matching the speed of a microprocessor to potentially slower external system components. A master clock signal is communicated to a clock generator on the processor chip. The clock generator provides at least one external clock signal, which is communicated to various portions of the system. The clock generator includes programmable clock division circuitry that allows the external clock signal to be generated at any selected one of a plurality of fractions of the master clock frequency. The data pattern (the particular cycles in a sequence during which the processor outputs a data word as part of a multiple-data-word sequence) is programmable independently of the external clock programming.
摘要翻译： 将微处理器速度与潜在较慢的外部系统组件相匹配的技术。 主时钟信号被传送到处理器芯片上的时钟发生器。 时钟发生器提供至少一个外部时钟信号，其被传送到系统的各个部分。 时钟发生器包括可编程时钟分频电路，其允许外部时钟信号以主时钟频率的多个分数中的任何选定的一个产生。 数据模式（处理器输出数据字作为多数据字序列的一部分的序列中的特定周期）可独立于外部时钟编程而编程。
-
公开(公告)号：US5317601A
公开(公告)日：1994-05-31
申请号：US933467
申请日：1992-08-21
CPC分类号： H03K5/15026 , G06F1/10 , H03K5/1502
摘要： Techniques for providing a number of precisely synchronized clock signals at a number of different frequencies at each of a plurality of locations on a chip. A number of synchronized clock signals are generated at an initial location on the chip, and distributed to the various locations with relative delay times that are equal to within a precision, which may be less than the ultimate precision required. A single synchronization signal is also generated at the initial location, and is distributed to the remote locations with delay times that are equal to each other to a precision that corresponds to the precision required of all the clock signals. Separate synchronization circuitry at each remote location receives the clock signals and the synchronization signal, and resynchronizes the clock signals to the precision with which the synchronization signal was distributed. The set of lines is configured as a tree structure. The clock generation system has a cycle-down mode wherein all the clock frequencies are divided by a desired divisor. The frequency division occurs in response to a cycle-down signal, but the different clock frequencies are not switched until all have their rising edges aligned. The result is that the state of the machine is preserved when the clocks are cycled down.
摘要翻译： 用于在芯片上的多个位置的每一个处提供多个不同频率的精确同步的时钟信号的技术。 在芯片上的初始位置处产生多个同步的时钟信号，并将其分配到具有等于精度内的相对延迟时间的各个位置，其可能小于所需的最终精度。 在初始位置也产生单个同步信号，并且分配给具有彼此相等的延迟时间的远程位置以对应于所有时钟信号所需的精度的精度。 每个远程位置处的独立同步电路接收时钟信号和同步信号，并将时钟信号重新同步到同步信号分配的精度。 该行的行被配置为一个树结构。 时钟发生系统具有周期下降模式，其中所有时钟频率被除以希望的除数。 频率分频发生在响应周期信号的情况下，但不同的时钟频率不被切换，直到所有的上升沿都对齐为止。 结果是当时钟循环下来时机器的状态被保留。
-
公开(公告)号：US5027270A
公开(公告)日：1991-06-25
申请号：US255791
申请日：1988-10-11
CPC分类号： G06F9/3814 , G06F12/0859 , G06F9/3802
摘要： A processor controlled interface between a processor, instruction cache, and main memory provides for simultaneously refilling the cache with an instruction block from main memory and processing the instructions in the block while they are being written to the cache.
摘要翻译： 处理器，指令高速缓存和主存储器之间的处理器控制的接口提供用于从主存储器中的指令块同时重新填充高速缓存并且在块被写入高速缓存时处理该块中的指令。
-
5.发明授权Apparatus, method and system for providing AC line power to lighting devices 有权用于向照明装置提供交流线路电力的装置，方法和系统公开(公告)号：US08410717B2
公开(公告)日：2013-04-02
申请号：US12729081
申请日：2010-03-22
申请人： Anatoly Shteynberg , Dongsheng Zhou , Harry Rodriguez , Mark Eason , Bradley M. Lehman , Stephen F. Dreyer , Thomas J. Riordan
发明人： Anatoly Shteynberg , Dongsheng Zhou , Harry Rodriguez , Mark Eason , Bradley M. Lehman , Stephen F. Dreyer , Thomas J. Riordan
IPC分类号： G05F1/00
CPC分类号： H05B33/083 , H05B33/0812 , Y02B20/343 , Y02B20/345
摘要： An apparatus, method, and system are disclosed for providing AC line power to lighting devices such as light emitting diodes (“LEDs”). A representative apparatus comprises: a plurality of LEDs coupled in series to form a first plurality of segments of LEDs; a plurality of switches coupled to the plurality of segments of LEDs to switch a selected segment into or out of a series LED current path in response to a control signal; a current sensor; and a controller which, in response to a first parameter and during a first part of an AC voltage interval, generates a first control signal to switch a corresponding segment of LEDs into the series LED current path; and during a second part of the AC voltage interval, generates a second control signal to switch the corresponding segment of LEDs out of the first series LED current path.
摘要翻译： 公开了一种用于向诸如发光二极管（LED）的照明装置提供AC线电力的装置，方法和系统。 代表性装置包括：串联耦合以形成LED的第一多个段的多个LED; 耦合到所述多个LED段的多个开关，以响应于控制信号将所选择的段切换到串联LED电流路径中或从串联LED电流路径中切换出; 电流传感器; 以及控制器，响应于第一参数和在AC电压间隔的第一部分期间产生第一控制信号以将相应的LED段切换到串联LED电流路径中; 并且在交流电压间隔的第二部分期间产生第二控制信号，以将相应的LED段切断出第一串联LED电流路径。
-
公开(公告)号：US5590294A
公开(公告)日：1996-12-31
申请号：US449588
申请日：1995-05-24
申请人： Sunil Mirapuri , Thomas J. Riordan
发明人： Sunil Mirapuri , Thomas J. Riordan
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3857 , G06F9/3861
摘要： A method and apparatus for restarting an instruction processing pipeline after servicing one or more interlock processing faults. A pipeline architecture is defined in which processing interdependencies (such as instruction latencies, resource conflicts, cache accesses, virtual address translations and sign extend operations) are presumed not to be present so as to increase pipeline throughput. Interdependencies which actually occur appear as processing faults which then are serviced. At the completion of the servicing, pipeline restarting operations occur, during which the portions of the pipeline which are invalidated are preloaded. Preloading includes backing-up the invalidated stages and re-executing such stages with corrected information so as to fill the pipeline. The pipeline portions (e.g., stages) which are invalidated are determined by the type of processing fault which occurs. Upon completion of preloading, normal instruction pipeline processing resumes.
摘要翻译： 一种在维修一个或多个互锁处理故障之后重新启动指令处理流水线的方法和装置。 定义了流水线架构，其中假设处理相互依赖关系（例如指令延迟，资源冲突，高速缓存访问，虚拟地址转换和符号扩展操作）不存在，以便增加流水线吞吐量。 实际发生的相互依赖性表现为处理故障，然后进行维修。 在完成维修时，发生管道重新启动操作，在此期间管道的无效部分被预加载。 预加载包括备份无效阶段，并用纠正的信息重新执行这些阶段，以填补管道。 无效的流水线部分（例如，级）由发生的处理故障的类型确定。 完成预加载后，恢复正常指令流水线处理。
-
7.发明授权Processor with an efficient translation lookaside buffer which uses previous address computation results 失效具有高效翻译后备缓冲器的处理器，其使用先前的地址计算结果
公开(公告)号：US5953748A
公开(公告)日：1999-09-14
申请号：US732862
申请日：1996-10-15
申请人： Thomas J. Riordan
发明人： Thomas J. Riordan
CPC分类号： G06F12/1027 , G06F2212/681
摘要： A structure and a method are provided in a table lookaside buffer (TLB) for translating a virtual memory address to a physical memory address. The virtual memory address is computed by adding to a base address an offset value. In the TLB of the present invention, each entry of the TLB is stored a previous base address, a partial sum of the previous virtual memory address computation, the sign bit of the previous offset value, and the value of the carry bit at the position of the sign bit of the previous offset value in the previous virtual memory address computation. The present invention is especially applicable to a data TLB used in conjunction with a two-way set associative data cache memory.
摘要翻译： 在用于将虚拟存储器地址转换为物理存储器地址的表后侧缓冲器（TLB）中提供了一种结构和方法。 通过将基址添加到偏移值来计算虚拟存储器地址。 在本发明的TLB中，TLB的每个条目被存储在先前的基地址，先前虚拟存储器地址计算的部分和，先前偏移值的符号位和位置上的进位位的值 的前一个虚拟内存地址计算中的先前偏移值的符号位。 本发明特别适用于与双向组关联数据高速缓冲存储器结合使用的数据TLB。
-
8.发明授权Dual byte order computer architecture a functional unit for handling data sets with differnt byte orders 失效双字节顺序计算机体系结构用于处理具有不同字节顺序的数据集的功能单元
公开(公告)号：US4959779A
公开(公告)日：1990-09-25
申请号：US277406
申请日：1988-11-28
摘要： A CPU or other function unit is disclosed which follows one data ordering scheme internally, and in which incoming and/or outgoing data pass through a data order conversion unit for adapting it to a selectable external data ordering scheme. The means for specifying the external data ordering scheme is accessible from outside the physical package(s) in which the functional unit is housed. The data order conversion unit may comprise a load aligner and/or a store aligner, one or both of which may comprise means for shifting informational units of a smaller size within informational units of a larger size. The shift amount may derive from the low order address bits and may be altered depending on the external data ordering means selected.
摘要翻译： 公开了一种CPU或其他功能单元，其在内部遵循一个数据排序方案，并且其中输入和/或输出数据通过数据顺序转换单元以将其适配成可选择的外部数据排序方案。 用于指定外部数据排序方案的装置可以从容纳功能单元的物理包的外部访问。 数据订单转换单元可以包括负载对准器和/或存储对准器，其中的一个或两个可以包括用于在较大尺寸的信息单元内移动更小尺寸的信息单元的装置。 移位量可以从低位地址位导出，并且可以根据所选择的外部数据排序装置而改变。
-
9.发明授权Apparatus, method and system for providing AC line power to lighting devices 有权用于向照明装置提供交流线路电力的装置，方法和系统公开(公告)号：US08324840B2
公开(公告)日：2012-12-04
申请号：US12478293
申请日：2009-06-04
申请人： Anatoly Shteynberg , Dongsheng Zhou , Harry Rodriguez , Mark Eason , Bradley M. Lehman , Stephen F. Dreyer , Thomas J. Riordan
发明人： Anatoly Shteynberg , Dongsheng Zhou , Harry Rodriguez , Mark Eason , Bradley M. Lehman , Stephen F. Dreyer , Thomas J. Riordan
CPC分类号： H05B33/083 , H05B33/0845 , H05B33/089
摘要： An apparatus, method, and system are disclosed for providing AC line power to lighting devices such as light emitting diodes (“LEDs”). A representative apparatus comprises: a plurality of LEDs coupled in series to form a first plurality of segments of LEDs coupled in series; a plurality of switches coupled to the plurality of segments of LEDs to switch a selected segment into or out of a series LED current path in response to a control signal; a memory; and a controller which, in response to a first parameter and during a first part of an AC voltage interval, determines and stores in the memory a value of a second parameter and generates a first control signal to switch a corresponding segment of LEDs into the series LED current path, and during a second part of the AC voltage interval, when a current value of the second parameter is substantially equal to the stored value, generates a second control signal to switch a corresponding segment of LEDs out of the first series LED current path.
摘要翻译： 公开了一种用于向诸如发光二极管（LED）的照明装置提供AC线电力的装置，方法和系统。 代表性装置包括：串联耦合的多个LED以形成串联耦合的第一多个LED段; 耦合到所述多个LED段的多个开关，以响应于控制信号将所选择的段切换到串联LED电流路径中或从串联LED电流路径中切换出; 记忆 以及控制器，其响应于第一参数并且在AC电压间隔的第一部分期间确定并存储在存储器中的第二参数的值，并且生成第一控制信号，以将相应的LED段切换成系列 LED电流路径，并且在交流电压间隔的第二部分期间，当第二参数的电流值基本上等于存储值时，产生第二控制信号以将相应的LED段切换出第一串联LED电流 路径。
-
10.发明申请Apparatus, Method and System for Providing AC Line Power to Lighting Devices 有权为照明设备提供交流线路电源的设备，方法和系统公开(公告)号：US20100308738A1
公开(公告)日：2010-12-09
申请号：US12729081
申请日：2010-03-22
申请人： Anatoly Shteynberg , Dongsheng Zhou , Harry Rodriguez , Mark Eason , Bradley M. Lehman , Stephen F. Dreyer , Thomas J. Riordan
发明人： Anatoly Shteynberg , Dongsheng Zhou , Harry Rodriguez , Mark Eason , Bradley M. Lehman , Stephen F. Dreyer , Thomas J. Riordan
IPC分类号： H05B37/02
CPC分类号： H05B33/083 , H05B33/0812 , Y02B20/343 , Y02B20/345
摘要： An apparatus, method and system are disclosed for providing AC line power to lighting devices such as light emitting diodes (“LEDs”). An exemplary apparatus comprises: a plurality of LEDs coupled in series to form a first plurality of segments of LEDs; a plurality of switches coupled to the plurality of segments of LEDs to switch a selected segment into or out of a series LED current path in response to a control signal; a current sensor; and a controller which, in response to a first parameter and during a first part of an AC voltage interval, generates a first control signal to switch a corresponding segment of LEDs into the series LED current path; and during a second part of the AC voltage interval, generates a second control signal to switch a corresponding segment of LEDs out of the first series LED current path.
摘要翻译： 公开了一种用于向例如发光二极管（“LED”）等照明装置提供AC线电力的装置，方法和系统。 示例性装置包括：串联耦合以形成LED的第一多个段的多个LED; 耦合到所述多个LED段的多个开关，以响应于控制信号将所选择的段切换到串联LED电流路径中或从串联LED电流路径中切换出; 电流传感器; 以及控制器，响应于第一参数和在AC电压间隔的第一部分期间产生第一控制信号以将相应的LED段切换到串联LED电流路径中; 并且在交流电压间隔的第二部分期间，产生第二控制信号，以将相应的LED段切断出第一串联LED电流路径。
-
-
-
-
-
-
-
-
-
搜索结果
17 条记录 (耗时 0.027 秒)
