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1.发明授权Cache memory architecture with system controller device that compares cache tags to memory addresses received from microprocessor 有权具有系统控制器设备的高速缓存存储器架构，将缓存标签与从微处理器接收的存储器地址进行比较公开(公告)号：US07243192B2
公开(公告)日：2007-07-10
申请号：US11426758
申请日：2006-06-27
IPC分类号： G06F12/10
CPC分类号： G06F12/0802
摘要： A single memory element, which may consist of general purpose SRAM chips, implements both tag and data cache memory functions, resulting in an efficient, low cost implementation of high speed external cache memory. In one embodiment, a bank of general purpose RAM used by a microprocessor as an external cache memory stores both cache tags and cache data in separate memory locations. During a read operation, the microprocessor retrieves a cache tag from the bank of general purpose RAM before retrieving corresponding cache data therefrom, and compares the cache tag to a memory address to assess whether requested data resides in the cache memory. The comparison may also be performed concurrently by a system controller device, which may abort the main memory access if a cache hit is detected.
摘要翻译： 可以由通用SRAM芯片组成的单个存储器元件实现标签和数据高速缓存存储器功能，导致高速外部高速缓冲存储器的高效，低成本实现。 在一个实施例中，由微处理器使用的一组通用RAM作为外部高速缓冲存储器将缓存标签和高速缓存数据都存储在单独的存储器位置中。 在读取操作期间，微处理器从通用RAM库中检索缓存标签，然后从其中检索相应的缓存数据，并将高速缓存标签与存储器地址进行比较，以评估所请求的数据是否驻留在高速缓冲存储器中。 该比较还可以由系统控制器设备同时执行，如果检测到高速缓存命中，则可以中止主存储器访问。
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2.发明授权Processor chip having on-chip circuitry for generating a programmable external clock signal and for controlling data patterns 失效具有用于产生可编程外部时钟信号并用于控制数据模式的片上电路的处理器芯片
公开(公告)号：US5734877A
公开(公告)日：1998-03-31
申请号：US715246
申请日：1996-09-19
CPC分类号： G06F1/08
摘要： Techniques for matching the speed of a microprocessor to potentially slower external system components. A master clock signal is communicated to a clock generator on the processor chip. The clock generator provides at least one external clock signal, which is communicated to various portions of the system. The clock generator includes programmable clock division circuitry that allows the external clock signal to be generated at any selected one of a plurality of fractions of the master clock frequency. The data pattern (the particular cycles in a sequence during which the processor outputs a data word as part of a multiple-data-word sequence) is programmable independently of the external clock programming.
摘要翻译： 将微处理器速度与潜在较慢的外部系统组件相匹配的技术。 主时钟信号被传送到处理器芯片上的时钟发生器。 时钟发生器提供至少一个外部时钟信号，其被传送到系统的各个部分。 时钟发生器包括可编程时钟分频电路，其允许外部时钟信号以主时钟频率的多个分数中的任何选定的一个产生。 数据模式（处理器输出数据字作为多数据字序列的一部分的序列中的特定周期）可独立于外部时钟编程而编程。
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公开(公告)号：US07130968B2
公开(公告)日：2006-10-31
申请号：US10732998
申请日：2003-12-11
IPC分类号： G06F12/10
CPC分类号： G06F12/0802
摘要： A single memory element, which may consist of general purpose SRAM chips, is used to implement both tag and data cache memory functions, resulting in an efficient, low cost implementation of high speed external cache memory. In one embodiment, a bank of general purpose random access memory used by a microprocessor as an external cache memory stores both cache tags and cache data in separate memory locations. During a read operation, the microprocessor retrieves a cache tag from the bank of general purpose random access memory before retrieving corresponding cache data therefrom, and compares the cache tag to a memory address to assess whether requested data resides within the cache memory. The microprocessor preferably accesses the bank of general purpose random access memory using a memory mapping function which maps the memory address into a cache tag address and a cache data address.
摘要翻译： 可以由通用SRAM芯片组成的单个存储器元件用于实现标签和数据高速缓冲存储器功能，从而实现高速外部高速缓冲存储器的高效，低成本实现。 在一个实施例中，由微处理器使用的一组通用随机存取存储器作为外部高速缓冲存储器将缓存标签和高速缓存数据都存储在单独的存储器位置中。 在读取操作期间，微处理器从通用随机存取存储器库中检索高速缓存标签，然后从其中检索相应的高速缓存数据，并将缓存标签与存储器地址进行比较，以评估所请求的数据是否驻留在高速缓冲存储器中。 微处理器优选地使用将存储器地址映射到高速缓存标签地址和高速缓存数据地址的存储器映射功能访问通用随机存取存储器组。
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4.发明授权Processor chip for using an external clock to generate an internal clock and for using data transmit patterns in combination with the internal clock to control transmission of data words to an external memory 失效处理器芯片，用于使用外部时钟来产生内部时钟，并使用与内部时钟相结合的数据传输模式来控制数据字传输到外部存储器
公开(公告)号：US5978926A
公开(公告)日：1999-11-02
申请号：US36684
申请日：1998-03-09
IPC分类号： G06F1/08
CPC分类号： G06F1/08
摘要： Techniques for matching the speed of a microprocessor to potentially slower external system components. A master clock signal is communicated to a clock generator on the processor chip. The clock generator provides at least one external clock signal, which is communicated to various portions of the system. The clock generator includes programmable clock division circuitry that allows the external clock signal to be generated at any selected one of a plurality of fractions of the master clock frequency. The data pattern (the particular cycles in a sequence during which the processor outputs a data word as part of a multiple-data-word sequence) is programmable independently of the external clock programming.
摘要翻译： 将微处理器速度与潜在较慢的外部系统组件相匹配的技术。 主时钟信号被传送到处理器芯片上的时钟发生器。 时钟发生器提供至少一个外部时钟信号，其被传送到系统的各个部分。 时钟发生器包括可编程时钟分频电路，其允许外部时钟信号以主时钟频率的多个分数中的任何选定的一个产生。 数据模式（处理器输出数据字作为多数据字序列的一部分的序列中的特定周期）可独立于外部时钟编程而编程。
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5.发明授权Apparatus for detecting any single bit error, detecting any two bit error, and detecting any three or four bit error in a group of four bits for a 25- or 64-bit data word 失效用于检测任何单个位错误，检测任何两个位错误以及检测25位或64位数据字的四位组中的任何三位或四位错误的装置
公开(公告)号：US5491702A
公开(公告)日：1996-02-13
申请号：US918819
申请日：1992-07-22
申请人： John R. Kinsel
发明人： John R. Kinsel
CPC分类号： G06F11/1028 , H03M13/00 , H03M13/51
摘要： An error detection system wherein 64 bits of data word are protected by 8 check bits which yield 8-bit syndromes. Single-bit errors are indicated by syndromes that contain exactly three "1"s or by syndromes that contain exactly five "1"s in which bits 0-3 or 4-7 of the syndrome are all "1." Single-bit errors that occur from faulty check bits are indicated by syndromes that contain exactly one "1." All two-bit errors, and four-bit errors within a nibble, are indicated by syndromes that contain an even number of "1"s (i.e., an even number of "1"s). Three-bit errors within a nibble are indicated by syndromes that contain five "1"s in which bits 0-3 of the syndrome and bits 4-7 of the syndrome are not all "1." Four-bit errors within a nibble are indicated by syndromes that contain four "1"s. In another embodiment of the invention, 25 bits of data word are protected by 7 check bits yielding 7-bit syndromes. Single-bit errors are indicated by syndromes that contain exactly three "1" s except single-bit errors that occur from faulty check bits are indicated by syndromes that contain exactly one "1". Two-bit errors are indicated by syndromes that contain an even number of "1"s, and three-bit errors within a nibble are indicated by syndromes that contain five "1"s or seven "1"s. Four-bit errors within a nibble are indicated by syndromes that contain four "1"s or six "1"s.
摘要翻译： 一种错误检测系统，其中64位数据字由8个校验位保护，产生8位校正位。 单位错误由完全包含三个“1”的综合征或完全包含正好五个“1”的综合征指示，其中综合征的0-3或4-7位全部为“1”。 由错误检查位发生的单位错误由正好包含一个“1”的综合征指示。 半字节内的所有2位错误和4位错误由包含偶数“1”（即偶数“1”）的综合征指示。 一个半字节内的三位错误由包含五个“1”的综合征指示，其中综合征的位0-3和综合征的位4-7不全为“1”。 半字节内的四位错误由包含四个“1”的综合征指示。 在本发明的另一个实施例中，25位数据字由7个检查位保护，产生7位综合征。 单位错误由完全包含三个“1”的综合征指示，除了错误检查位发生的单位错误由正好包含一个“1”的综合征指示。 两位错误由包含偶数“1”的综合征指示，并且半字节内的三位错误由包含五个“1”或七“1”的综合征指示。 四位内的四位错误由包含四个“1”或六个“1”的综合征指示。
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