公开(公告)号：US20060076601A1

公开(公告)日：2006-04-13

申请号：US10980225

申请日：2004-11-04

Applicant: Rui-Yuan Hon ,  Tony Chien

Inventor： Rui-Yuan Hon ,  Tony Chien

IPC: H01L29/94 ,  H01L21/8242

CPC classification number: H01L27/0207 ,  H01L27/10867 ,  H01L27/10888 ,  Y10S257/905

Abstract: A dynamic random access memory structure is provided, each active area of a memory unit cell is distributed individually in a substrate, and deep trench patterns are designed to have a checkerboard-like arrangement in the substrate. Also, there is a constant space between each deep trench pattern in a row. Further, long bit line contact plugs are located to electrically connect active areas of two diagonally neighbor memory unit cells, and a contact hole is formed on each long bit line contact plug to enable bit lines contact the long bit line contact plugs so two diagonally neighbor memory unit cells are controlled by the same bit line.

Abstract translation: 提供了动态随机存取存储器结构，存储单元单元的每个有源区域分别分布在衬底中，并且深沟槽图案被设计为在衬底中具有棋盘状布置。 此外，在一排中的每个深沟槽图案之间存在恒定的空间。 此外，长位线接触插头被定位成电连接两个对角相邻存储单元电池的有源区，并且在每个长位线接触插塞上形成接触孔，以使位线接触长位线接触插塞，使得两个对角线邻近 存储器单元由相同的位线控制。

公开(公告)号：US07091544B2

公开(公告)日：2006-08-15

申请号：US10980225

申请日：2004-11-04

Applicant: Rui-Yuan Hon ,  Tony Chien

Inventor： Rui-Yuan Hon ,  Tony Chien

IPC: H01L27/108

CPC classification number: H01L27/0207 ,  H01L27/10867 ,  H01L27/10888 ,  Y10S257/905

Abstract: A dynamic random access memory structure is provided, each active area of a memory unit cell is distributed individually in a substrate, and deep trench patterns are designed to have a checkerboard-like arrangement in the substrate. Also, there is a constant space between each deep trench pattern in a row. Further, long bit line contact plugs are located to electrically connect active areas of two diagonally neighbor memory unit cells, and a contact hole is formed on each long bit line contact plug to enable bit lines contact the long bit line contact plugs so two diagonally neighbor memory unit cells are controlled by the same bit line.

Abstract translation: 提供了动态随机存取存储器结构，存储单元单元的每个有源区域分别分布在衬底中，并且深沟槽图案被设计为在衬底中具有棋盘状布置。 此外，在一排中的每个深沟槽图案之间存在恒定的空间。 此外，长位线接触插头被定位成电连接两个对角相邻存储单元电池的有源区，并且在每个长位线接触插塞上形成接触孔，以使位线接触长位线接触插塞，使得两个对角线相邻 存储器单元由相同的位线控制。

公开(公告)号：US06936521B2

公开(公告)日：2005-08-30

申请号：US10750805

申请日：2004-01-02

Applicant: Tony Chien

Inventor： Tony Chien

IPC: G03F9/00 ,  H01L23/544 ,  H01L21/76

CPC classification number: G03F9/7084 ,  G03F9/7076 ,  G03F9/708

Abstract: An alignment mark is made of at least two nonparallel trenches having two reducing-width-to-zero ends. The displacement bias error, produced by a process bias error, of the centerlines of the trenches is zero where the width of the two trenches is zero. Hence, the alignment target on a substrate can be reproduced.

Abstract translation: 对准标记由至少两个具有两个减小宽度到零端的不平行沟槽制成。 由沟槽中心线产生的位移偏移误差为零，两个沟槽的宽度为零。 因此，可以再现衬底上的取向靶。

公开(公告)号：US20050023709A1

公开(公告)日：2005-02-03

申请号：US10750805

申请日：2004-01-02

Applicant: Tony Chien

Inventor： Tony Chien

IPC: G03F9/00 ,  H01L23/544 ,  H01L21/76

CPC classification number: G03F9/7084 ,  G03F9/7076 ,  G03F9/708

Abstract: An alignment mark is made of at least two nonparallel trenches having two reducing-width-to-zero ends. The displacement bias error, produced by a process bias error, of the centerlines of the trenches is zero where the width of the two trenches is zero. Hence, the alignment target on a substrate can be reproduced.

公开(公告)号：USD355231S

公开(公告)日：1995-02-07

申请号：US7663

申请日：1993-04-29

Applicant: Tony Chien

Designer： Tony Chien