公开(公告)号：USRE47093E1

公开(公告)日：2018-10-23

申请号：US15292073

申请日：2016-10-12

Applicant: Toshiba Memory Corporation

Inventor： Hiroshi Tokue ,  Ikuo Yoneda ,  Ryoichi Inanami

IPC: B29C59/02 ,  G01B11/10 ,  B29C43/02 ,  B82Y10/00

Abstract: An imprint pattern forming method includes contacting a template with a pattern in a front surface with an imprint material formed in a substrate to fill the imprint material into the pattern, curing the imprint material filled in the pattern to form an imprint material pattern, and after forming the imprint material pattern, separating the template from the imprint material pattern while applying pressure to the back surface of the template.

公开(公告)号：USRE47271E1

公开(公告)日：2019-03-05

申请号：US15173516

申请日：2016-06-03

Applicant: Toshiba Memory Corporation

Inventor： Shinji Mikami ,  Ryoichi Inanami

IPC: B41J2/01 ,  B41J2/00 ,  G03F7/00 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/67

Abstract: Certain embodiments provide an imprint recipe creating device comprising first to fifth creation units. The first creation unit creates inside-standard-shot information by use of filling amount information and residual film thickness information. The second creation unit creates first inside-substrate-surface information by use of shot position information, edge information, and the inside-standard-shot information. The third creation unit creates first correction information by use of unevenness information indicating unevenness in a substrate and unevenness distribution information indicating variations in depth of the unevenness inside the substrate surface. The fourth creation unit creates second correction information by use of post-process information indicating the variations in processing size. The fifth creation unit synthesizes the first inside-substrate-surface information, the first correction information and the second correction information, to create second inside-substrate-surface information.

公开(公告)号：USRE46901E1

公开(公告)日：2018-06-19

申请号：US14883569

申请日：2015-10-14

Applicant: Toshiba Memory Corporation

Inventor： Yasuo Matsuoka ,  Takumi Ota ,  Ryoichi Inanami

IPC: G06F17/50 ,  G03F7/00 ,  B82Y10/00

CPC classification number: G06F17/30289 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002

Abstract: According to one embodiment, a plurality of test drop recipes are first created based on design data on a semiconductor integrated circuit. Based on a defect inspection result of a pattern of a hardening resin material, which is formed by pressing a template on which patterns of the semiconductor integrated circuit are formed onto the hardening resin material applied to a substrate to be processed by use of the test drop recipes, a drop recipe with least defects is selected per press position on the substrate to be processed from the test drop recipes. The selected drop recipes for respective press positions are collected per functional circuit block configuring the semiconductor integrated circuit, thereby to generate a drop recipe creation assistant database.