公开(公告)号：US20250072080A1

公开(公告)日：2025-02-27

申请号：US18372684

申请日：2023-09-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Yih Chen ,  Yi-Wen Chen ,  Chia-Chen Sun ,  Wei-Chung Sun ,  Wan-Ching Lee

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate structure on a substrate, forming a first spacer on the gate structure, forming a patterned mask on the gate structure and one side of the gate structure, removing the first spacer on another side of the gate structure, and then forming a source/drain region adjacent to two sides of the gate structure.

公开(公告)号：US20250048659A1

公开(公告)日：2025-02-06

申请号：US18367468

申请日：2023-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Yih Chen ,  Kuo-Hsing Lee ,  Chun-Hsien Lin

IPC: H01L29/66 ,  H01L27/06 ,  H01L29/78 ,  H01L29/94

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising a non-metal-oxide semiconductor capacitor (non-MOSCAP) region and a MOSCAP region, forming a first fin-shaped structure on the MOSCAP region, forming a doped layer on the substrate of the non-MOSCAP region and the first fin-shaped structure on the MOSCAP region, removing the doped layer on the non-MOSCAP region, and then performing an anneal process to drive dopants from the doped layer into the first fin-shaped structure.

公开(公告)号：US20250054880A1

公开(公告)日：2025-02-13

申请号：US18369207

申请日：2023-09-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin ,  Chang-Yih Chen

IPC: H01L23/00 ,  H01L21/768 ,  H10B61/00

Abstract: A method for fabricating a physically unclonable function (PUF) device includes the steps of firs providing a substrate comprising a magnetoresistive random access memory (MRAM) region, a PUF cell region, and a non-PUF cell region, forming a first metal interconnection on the MRAM region, forming a second metal interconnection on the PUF cell region, and forming a third metal interconnection on the non-PUF cell region. Preferably, the first metal interconnection and the second metal interconnection include patterns of different shapes and the first metal interconnection and the third metal interconnection include patterns of same shape.

公开(公告)号：US20250141701A1

公开(公告)日：2025-05-01

申请号：US18518567

申请日：2023-11-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Yih Chen ,  Kuo-Hsing Lee ,  Chun-Hsien Lin

IPC: H04L9/32 ,  H01L27/06 ,  H01L29/94

Abstract: A method for fabricating a physically unclonable function (PUF) device includes the steps of first providing a PUF cell array having a plurality of unit cells, in which each of the unit cells includes a transistor and a first metal-oxide semiconductor capacitor (MOSCAP) and a second MOSCAP coupled to the transistor. Next, a voltage is transmitted through the transistor to the first MOSCAP and the second MOSCAP and whether the first MOSCAP or the second MOSCAP reaches a breakdown is determined.

公开(公告)号：US20250063803A1

公开(公告)日：2025-02-20

申请号：US18368552

申请日：2023-09-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Yih Chen ,  Kuo-Hsing Lee ,  Chun-Hsien Lin ,  Kun-Szu Tseng ,  Sheng-Yuan Hsueh ,  Yao-Jhan Wang

IPC: H01L21/8234 ,  H01L27/06

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a non-metal-oxide semiconductor capacitor (non-MOSCAP) region and a MOSCAP region, forming a first fin-shaped structure on the MOSCAP region, performing a monolayer doping (MLD) process on the first fin-shaped structure, and then performing an anneal process for driving dopants into the first fin-shaped structure. Preferably, the MLD process is further accomplished by first performing a wet chemical doping process on the first fin-shaped structure and then forming a cap layer on the non-MOSCAP region and the MOSCAP region.

公开(公告)号：US20250056818A1

公开(公告)日：2025-02-13

申请号：US18367467

申请日：2023-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Yih Chen ,  Kuo-Hsing Lee ,  Chun-Hsien Lin

IPC: H01L29/94 ,  H01L27/06 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a bottom portion, a middle portion, a top portion, and a base portion between the bottom portion and the substrate. Preferably, the bottom portion is surrounded by a shallow trench isolation (STI), a gate oxide layer is disposed on the fin-shaped structure and the STI, a bottom surface of the gate oxide layer is higher than a top surface of the base portion, a width of a top surface of the bottom portion is greater than half the width of the bottom surface of the bottom portion, and a tip of the top portion includes a tapered portion.

公开(公告)号：US20240363430A1

公开(公告)日：2024-10-31

申请号：US18203654

申请日：2023-05-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Yi Wang ,  Wei-Che Chen ,  Hung-Chun Lee ,  Yun-Yang He ,  Wei-Hao Chang ,  Chang-Yih Chen ,  Kun-Szu Tseng ,  Yao-Jhan Wang ,  Ying-Hsien Chen

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0607 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/66545

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having an active region as the substrate includes a medium-voltage (MV) region and a low-voltage (LV) region, forming a first divot adjacent to one side of the active region, forming a second divot adjacent to another side of the active region, forming a first liner in the first divot and the second divot and on the substrate of the MV region and LV region, forming a second liner on the first liner, and then removing the second liner, the first liner, and the substrate on the LV region for forming a fin-shaped structure.

公开(公告)号：US20250159874A1

公开(公告)日：2025-05-15

申请号：US18531696

申请日：2023-12-07

Applicant: UNITED MICROELECTRONICS CORP

Inventor： Chang-Yih Chen ,  Kuo-Hsing Lee ,  Chun-Hsien Lin

IPC: H10B20/25

Abstract: A one-time programmable memory structure includes semiconductor substrate of a first conductivity type and a fin disposed on the semiconductor substrate. The fin extends along a first direction, wherein the fin includes a first portion and a second portion that is contiguous with the first portion. The first portion and the second portion have different cross-sectional profiles. A gate extends on the fin along a second direction. The gate partially overlaps the first portion of the fin and partially overlaps the second portion of the fin.

公开(公告)号：US20250142815A1

公开(公告)日：2025-05-01

申请号：US18519092

申请日：2023-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Yih Chen ,  Kuo-Hsing Lee ,  Chun-Hsien Lin ,  Wen-Chieh Chang ,  Kun-Szu Tseng ,  Sheng-Yuan Hsueh ,  Yao-Jhan Wang

IPC: H10B20/25

Abstract: A semiconductor device includes a substrate having a medium-voltage (MV) region and an one time programmable (OTP) capacitor region, a MV device on the MV region, and an OTP capacitor on the OTP capacitor region. Preferably, the MV device includes a first gate dielectric layer on the substrate, a first gate electrode on the first gate dielectric layer, and a shallow trench isolation (STI) adjacent to two sides of the first gate electrode. The OTP capacitor includes a fin-shaped structure on the substrate, a doped region in the fin-shaped structure, a second gate dielectric layer on the doped region, and a second gate electrode on the second gate dielectric layer.

公开(公告)号：US20250072015A1

公开(公告)日：2025-02-27

申请号：US18370402

申请日：2023-09-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Yih Chen ,  Kuo-Hsing Lee ,  Chun-Hsien Lin ,  Kun-Szu Tseng ,  Sheng-Yuan Hsueh ,  Yao-Jhan Wang

IPC: H01L29/94 ,  H01L27/06 ,  H01L29/66 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a non-metal-oxide semiconductor capacitor (non-MOSCAP) region and a MOSCAP region, forming a fin-shaped structure on the MOSCAP region, forming a shallow trench isolation (STI) around the substrate and the fin-shaped structure, performing a first etching process to remove part of the STI on the MOSCAP region, and then performing a second etching process to remove part of the STI on the non-MOSCAP region and the MOSCAP region.