公开(公告)号：US20200350199A1

公开(公告)日：2020-11-05

申请号：US16431684

申请日：2019-06-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Hsuan Chang ,  Hung-Chun Lee ,  Shu-Ming Yeh ,  Ting-An Chien ,  Bin-Siang Tsai

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/311

Abstract: A method for fabricating semiconductor device includes the steps of: forming a trench in a substrate; forming a pad layer adjacent to two sides of trench; forming a dielectric layer to fill the trench; and performing a dry etching process to remove the pad layer and part of the dielectric layer to form a shallow trench isolation (STI). Preferably, the dry etching process comprises a non-plasma etching process.

公开(公告)号：US20250015186A1

公开(公告)日：2025-01-09

申请号：US18227299

申请日：2023-07-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chun Lee ,  Chih-Yi Wang ,  Wei-Che Chen ,  Ya-Ting Hu ,  Yao-Jhan Wang ,  Kun-Szu Tseng ,  Feng-Yun Cheng ,  Shyan-Liang Chou

IPC: H01L29/78 ,  H01L25/16

Abstract: The invention provides a semiconductor structure, which comprises a middle/high voltage device region and a low voltage device region, a plurality of fin structures disposed in the low voltage device region, and a protruding part located at a boundary Between the middle/high voltage device region and the low voltage device region. A top surface of the protruding part is flat, and the top surface of the protruding part is aligned with a flat top surface of the middle/high voltage device region.

公开(公告)号：US20240363430A1

公开(公告)日：2024-10-31

申请号：US18203654

申请日：2023-05-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Yi Wang ,  Wei-Che Chen ,  Hung-Chun Lee ,  Yun-Yang He ,  Wei-Hao Chang ,  Chang-Yih Chen ,  Kun-Szu Tseng ,  Yao-Jhan Wang ,  Ying-Hsien Chen

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0607 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/66545

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having an active region as the substrate includes a medium-voltage (MV) region and a low-voltage (LV) region, forming a first divot adjacent to one side of the active region, forming a second divot adjacent to another side of the active region, forming a first liner in the first divot and the second divot and on the substrate of the MV region and LV region, forming a second liner on the first liner, and then removing the second liner, the first liner, and the substrate on the LV region for forming a fin-shaped structure.

公开(公告)号：US11114331B2

公开(公告)日：2021-09-07

申请号：US16431684

申请日：2019-06-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Hsuan Chang ,  Hung-Chun Lee ,  Shu-Ming Yeh ,  Ting-An Chien ,  Bin-Siang Tsai

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L21/311

Abstract: A method for fabricating semiconductor device includes the steps of: forming a trench in a substrate; forming a pad layer adjacent to two sides of trench; forming a dielectric layer to fill the trench; and performing a dry etching process to remove the pad layer and part of the dielectric layer to form a shallow trench isolation (STI). Preferably, the dry etching process comprises a non-plasma etching process.