公开(公告)号：US20210320109A1

公开(公告)日：2021-10-14

申请号：US16843864

申请日：2020-04-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fang-Sheng Chou ,  Ching Chang

IPC: H01L27/11 ,  G11C29/12

Abstract: The present invention provides a test key structure, the test key structure a substrate, a plurality of test key cells disposed on the substrate, wherein each test key cell includes a first gate structure arranged along a first direction (X-axis), a first diffusion region, a second diffusion region, a connection diffusion region and a share contact arranged along a second direction (Y-axis), wherein the first gate structure crosses over the first diffusion region to form a pull-up transistor (PU), the second gate structure crosses over the second diffusion region to form a pull-down transistor (PD), and wherein the plurality of share contacts and the plurality of connection diffusion regions of the plurality of test key cells are electrically connected to each other.

公开(公告)号：US10134744B1

公开(公告)日：2018-11-20

申请号：US15681444

申请日：2017-08-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Han Chen ,  Wei-Chi Chen ,  Ching Chang ,  Ming-Shing Chen ,  Chao-Hsien Wu ,  Chia-Hui Hwang ,  Lu-Ran Huang

IPC: G11C11/404 ,  H01L27/11 ,  H01L27/12 ,  G11C11/4097 ,  G11C11/417

Abstract: A semiconductor memory device includes a first inverter, a second inverter, a first and second inner access transistors, and a first and second outer access transistors. The first inverter includes a first pull-up transistor and a first pull-down transistor, the second inverter includes a second pull-up transistor (PL2) and a second pull-down transistor, and the first inverter and the second inverter forms a latch circuit. The first and second inner access transistors and the first and second outer access transistors are electrically connected to the latch circuit, and channel widths of the second inner access transistor and the second outer access transistor are different from each other.