公开(公告)号：US20140357050A1

公开(公告)日：2014-12-04

申请号：US13907996

申请日：2013-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： JI FENG ,  XIAOQING XU ,  Hailong Gu ,  Ying-Tu Chen ,  JINGLING WANG

IPC: H01L21/762 ,  H01L21/768

CPC classification number: H01L21/76229 ,  H01L21/76898

Abstract: A method of forming an isolation structure and a through silicon via includes the following steps. First, at least a first trench and at least a second trench are formed in the substrate by a single etch step. Then, an insulating layer is formed to simultaneously fill up the first trench and cover a sidewall and a bottom of the second trench. After that, a conductive layer is formed to fill in the second trench. Subsequently, the insulating layer and the conductive layer on a front side of the substrate are removed. Later, a back side of the substrate is thinned to expose the conductive layer in the second trench. The insulating layer in the first trench serves as an insulating filling, and the insulating layer on the sidewall of the second trench serves as a liner of the through silicon via.

Abstract translation: 形成隔离结构和通硅通孔的方法包括以下步骤。 首先，通过单个蚀刻步骤在衬底中形成至少第一沟槽和至少第二沟槽。 然后，形成绝缘层以同时填充第一沟槽并覆盖第二沟槽的侧壁和底部。 之后，形成导电层以填充第二沟槽。 随后，去除衬底正面上的绝缘层和导电层。 之后，使基板的背面变薄以露出第二沟槽中的导电层。 第一沟槽中的绝缘层用作绝缘填充物，并且第二沟槽的侧壁上的绝缘层用作穿硅通孔的衬垫。

公开(公告)号：US20220262671A1

公开(公告)日：2022-08-18

申请号：US17737011

申请日：2022-05-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yunfei Li ,  JI FENG ,  GUOHAI ZHANG ,  CHING HWA TEY

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L21/02

Abstract: A transistor structure with an air gap includes a substrate. A transistor is disposed on the substrate. An etching stop layer covers and contacts the transistor and the substrate. A first dielectric layer covers and contacts the etching stop layer. A second dielectric layer covers the first dielectric layer. A trench is disposed on the gate structure and within the first dielectric layer and the second dielectric layer. A width of the trench within the second dielectric layer is smaller than a width of the trench within the first dielectric layer. A filling layer is disposed within the trench and covers the top surface of the second dielectric layer. An air gap is formed within the filling layer.

公开(公告)号：US20220139762A1

公开(公告)日：2022-05-05

申请号：US17133652

申请日：2020-12-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yunfei Li ,  JI FENG ,  GUOHAI ZHANG ,  CHING HWA TEY

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L21/02

Abstract: A transistor structure with an air gap includes a substrate. A transistor is disposed on the substrate. An etching stop layer covers and contacts the transistor and the substrate. A first dielectric layer covers and contacts the etching stop layer. A second dielectric layer covers the first dielectric layer. A trench is disposed on the gate structure and within the first dielectric layer and the second dielectric layer. A width of the trench within the second dielectric layer is smaller than a width of the trench within the first dielectric layer. A filling layer is disposed within the trench and covers the top surface of the second dielectric layer. An air gap is formed within the filling layer.

公开(公告)号：US20210134653A1

公开(公告)日：2021-05-06

申请号：US16673929

申请日：2019-11-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： JI FENG ,  Yunfei Li ,  GUOHAI ZHANG ,  CHING HWA TEY ,  JINGLING WANG

IPC: H01L21/762 ,  H01L21/311 ,  H01L21/265

Abstract: A method of forming a semiconductor device includes following steps. Firstly, a substrate is provided and the substrate has a first semiconductor layer formed thereon. Next, an isolating structure is formed in the first semiconductor layer, and a sacrificial layer is formed on the first semiconductor layer by consuming a top portion of the first semiconductor layer. Then, the sacrificial layer is removed to form a second semiconductor layer, and a portion of the isolating structure is also removed to form a shallow trench isolation (STI), with a top surface of the shallow trench isolation being substantially coplanar with a top surface of the second semiconductor layer.