公开(公告)号：US20240332067A1

公开(公告)日：2024-10-03

申请号：US18739344

申请日：2024-06-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yunfei Li ,  Ji Feng ,  Guohai Zhang ,  Ching Hwa Tey

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/7682 ,  H01L21/02063 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76895 ,  H01L23/5329 ,  H01L23/535

Abstract: A transistor structure with an air gap includes a substrate. A transistor is disposed on the substrate. An etching stop layer covers and contacts the transistor and the substrate. A first dielectric layer covers and contacts the etching stop layer. A second dielectric layer covers the first dielectric layer. A trench is disposed on the gate structure and within the first dielectric layer and the second dielectric layer. A width of the trench within the second dielectric layer is smaller than a width of the trench within the first dielectric layer. A filling layer is disposed within the trench and covers the top surface of the second dielectric layer. An air gap is formed within the filling layer.

公开(公告)号：US11127621B2

公开(公告)日：2021-09-21

申请号：US16673929

申请日：2019-11-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ji Feng ,  Yunfei Li ,  Guohai Zhang ,  Ching Hwa Tey ,  Jingling Wang

IPC: H01L21/762 ,  H01L21/76 ,  H01L21/311 ,  H01L21/265

Abstract: A method of forming a semiconductor device includes following steps. Firstly, a substrate is provided and the substrate has a first semiconductor layer formed thereon. Next, an isolating structure is formed in the first semiconductor layer, and a sacrificial layer is formed on the first semiconductor layer by consuming a top portion of the first semiconductor layer. Then, the sacrificial layer is removed to form a second semiconductor layer, and a portion of the isolating structure is also removed to form a shallow trench isolation (STI), with a top surface of the shallow trench isolation being substantially coplanar with a top surface of the second semiconductor layer.

公开(公告)号：US20220262671A1

公开(公告)日：2022-08-18

申请号：US17737011

申请日：2022-05-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yunfei Li ,  JI FENG ,  GUOHAI ZHANG ,  CHING HWA TEY

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L21/02

Abstract: A transistor structure with an air gap includes a substrate. A transistor is disposed on the substrate. An etching stop layer covers and contacts the transistor and the substrate. A first dielectric layer covers and contacts the etching stop layer. A second dielectric layer covers the first dielectric layer. A trench is disposed on the gate structure and within the first dielectric layer and the second dielectric layer. A width of the trench within the second dielectric layer is smaller than a width of the trench within the first dielectric layer. A filling layer is disposed within the trench and covers the top surface of the second dielectric layer. An air gap is formed within the filling layer.

公开(公告)号：US11355389B2

公开(公告)日：2022-06-07

申请号：US17133652

申请日：2020-12-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yunfei Li ,  Ji Feng ,  Guohai Zhang ,  Ching Hwa Tey

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L21/02

Abstract: A transistor structure with an air gap includes a substrate. A transistor is disposed on the substrate. An etching stop layer covers and contacts the transistor and the substrate. A first dielectric layer covers and contacts the etching stop layer. A second dielectric layer covers the first dielectric layer. A trench is disposed on the gate structure and within the first dielectric layer and the second dielectric layer. A width of the trench within the second dielectric layer is smaller than a width of the trench within the first dielectric layer. A filling layer is disposed within the trench and covers the top surface of the second dielectric layer. An air gap is formed within the filling layer.

公开(公告)号：US12040224B2

公开(公告)日：2024-07-16

申请号：US17737011

申请日：2022-05-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yunfei Li ,  Ji Feng ,  Guohai Zhang ,  Ching Hwa Tey

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/7682 ,  H01L21/02063 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76895 ,  H01L23/5329 ,  H01L23/535

Abstract: A transistor structure with an air gap includes a substrate. A transistor is disposed on the substrate. An etching stop layer covers and contacts the transistor and the substrate. A first dielectric layer covers and contacts the etching stop layer. A second dielectric layer covers the first dielectric layer. A trench is disposed on the gate structure and within the first dielectric layer and the second dielectric layer. A width of the trench within the second dielectric layer is smaller than a width of the trench within the first dielectric layer. A filling layer is disposed within the trench and covers the top surface of the second dielectric layer. An air gap is formed within the filling layer.

公开(公告)号：US20220139762A1

公开(公告)日：2022-05-05

申请号：US17133652

申请日：2020-12-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yunfei Li ,  JI FENG ,  GUOHAI ZHANG ,  CHING HWA TEY

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L21/02

Abstract: A transistor structure with an air gap includes a substrate. A transistor is disposed on the substrate. An etching stop layer covers and contacts the transistor and the substrate. A first dielectric layer covers and contacts the etching stop layer. A second dielectric layer covers the first dielectric layer. A trench is disposed on the gate structure and within the first dielectric layer and the second dielectric layer. A width of the trench within the second dielectric layer is smaller than a width of the trench within the first dielectric layer. A filling layer is disposed within the trench and covers the top surface of the second dielectric layer. An air gap is formed within the filling layer.

公开(公告)号：US20210134653A1

公开(公告)日：2021-05-06

申请号：US16673929

申请日：2019-11-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： JI FENG ,  Yunfei Li ,  GUOHAI ZHANG ,  CHING HWA TEY ,  JINGLING WANG

IPC: H01L21/762 ,  H01L21/311 ,  H01L21/265

Abstract: A method of forming a semiconductor device includes following steps. Firstly, a substrate is provided and the substrate has a first semiconductor layer formed thereon. Next, an isolating structure is formed in the first semiconductor layer, and a sacrificial layer is formed on the first semiconductor layer by consuming a top portion of the first semiconductor layer. Then, the sacrificial layer is removed to form a second semiconductor layer, and a portion of the isolating structure is also removed to form a shallow trench isolation (STI), with a top surface of the shallow trench isolation being substantially coplanar with a top surface of the second semiconductor layer.