公开(公告)号：US11121254B2

公开(公告)日：2021-09-14

申请号：US16572568

申请日：2019-09-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Bo-Shiun Chen ,  Chun-Jen Chen ,  Chung-Ting Huang ,  Chi-Hsuan Tang ,  Jhong-Yi Huang ,  Guan-Ying Wu

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/08 ,  H01L29/15 ,  H01L29/66

Abstract: A transistor with strained superlattices as source/drain regions includes a substrate. A gate structure is disposed on the substrate. Two superlattices are respectively disposed at two sides of the gate structure and embedded in the substrate. The superlattices are strained. Each of the superlattices is formed by a repeated alternating stacked structure including a first epitaxial silicon germanium and a second epitaxial silicon germanium. The superlattices serve as source/drain regions of the transistor.

公开(公告)号：US20200243664A1

公开(公告)日：2020-07-30

申请号：US16294877

申请日：2019-03-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chih Chuang ,  Chia-Jong Liu ,  Kuang-Hsiu Chen ,  Chung-Ting Huang ,  Chi-Hsuan Tang ,  Kai-Hsiang Wang ,  Bing-Yang Jiang ,  Yu-Lin Cheng ,  Chun-Jen Chen ,  Yu-Shu Lin ,  Jhong-Yi Huang ,  Chao-Nan Chen ,  Guan-Ying Wu

IPC: H01L29/66 ,  H01L29/423

Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided, in which the method includes the steps of forming a gate structure on a substrate, forming a spacer on a sidewall of the gate structure, forming two recesses adjacent to two sides of the spacer, performing a cleaning process to trim the spacer for forming a void between the spacer and the substrate, and forming two portions of an epitaxial layer in the two recesses. The semiconductor device preferably includes a cap layer on the two portions of the epitaxial layer as the cap layer includes a planar top surface and an inclined sidewall.

公开(公告)号：US12300743B2

公开(公告)日：2025-05-13

申请号：US18665600

申请日：2024-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chih Chuang ,  Chia-Jong Liu ,  Kuang-Hsiu Chen ,  Chung-Ting Huang ,  Chi-Hsuan Tang ,  Kai-Hsiang Wang ,  Bing-Yang Jiang ,  Yu-Lin Cheng ,  Chun-Jen Chen ,  Yu-Shu Lin ,  Jhong-Yi Huang ,  Chao-Nan Chen ,  Guan-Ying Wu

IPC: H01L29/66 ,  H01L29/423

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.

公开(公告)号：US20220069127A1

公开(公告)日：2022-03-03

申请号：US17033897

申请日：2020-09-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yu Chen ,  Bo-Lin Huang ,  Jhong-Yi Huang ,  Keng-Jen Lin ,  Yu-Shu Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/16

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming recesses adjacent to two sides of the gate structure, forming a buffer layer in the recesses, forming a first linear bulk layer on the buffer layer, forming a second linear bulk layer on the first linear bulk layer, forming a bulk layer on the second linear bulk layer, and forming a cap layer on the bulk layer.

公开(公告)号：US20240304705A1

公开(公告)日：2024-09-12

申请号：US18665600

申请日：2024-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chih Chuang ,  Chia-Jong Liu ,  Kuang-Hsiu Chen ,  Chung-Ting Huang ,  Chi-Hsuan Tang ,  Kai-Hsiang Wang ,  Bing-Yang Jiang ,  Yu-Lin Cheng ,  Chun-Jen Chen ,  Yu-Shu Lin ,  Jhong-Yi Huang ,  Chao-Nan Chen ,  Guan-Ying Wu

IPC: H01L29/66 ,  H01L29/423

CPC classification number: H01L29/6656 ,  H01L29/42364

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.

公开(公告)号：US20240266437A1

公开(公告)日：2024-08-08

申请号：US18635018

申请日：2024-04-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yu Chen ,  Bo-Lin Huang ,  Jhong-Yi Huang ,  Keng-Jen Lin ,  Yu-Shu Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/16

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L29/16

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming recesses adjacent to two sides of the gate structure, forming a buffer layer in the recesses, forming a first linear bulk layer on the buffer layer, forming a second linear bulk layer on the first linear bulk layer, forming a bulk layer on the second linear bulk layer, and forming a cap layer on the bulk layer.

公开(公告)号：US11990547B2

公开(公告)日：2024-05-21

申请号：US17033897

申请日：2020-09-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yu Chen ,  Bo-Lin Huang ,  Jhong-Yi Huang ,  Keng-Jen Lin ,  Yu-Shu Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/16

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L29/16

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming recesses adjacent to two sides of the gate structure, forming a buffer layer in the recesses, forming a first linear bulk layer on the buffer layer, forming a second linear bulk layer on the first linear bulk layer, forming a bulk layer on the second linear bulk layer, and forming a cap layer on the bulk layer.

公开(公告)号：US11545560B2

公开(公告)日：2023-01-03

申请号：US17160421

申请日：2021-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chih Chuang ,  Chia-Jong Liu ,  Kuang-Hsiu Chen ,  Chung-Ting Huang ,  Chi-Hsuan Tang ,  Kai-Hsiang Wang ,  Bing-Yang Jiang ,  Yu-Lin Cheng ,  Chun-Jen Chen ,  Yu-Shu Lin ,  Jhong-Yi Huang ,  Chao-Nan Chen ,  Guan-Ying Wu

IPC: H01L29/66 ,  H01L29/423

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer and a second spacer around the gate structure; forming a recess adjacent to two sides of the second spacer; performing a cleaning process to trim the second spacer for forming a void between the first spacer and the substrate; and forming an epitaxial layer in the recess.

公开(公告)号：US20210057579A1

公开(公告)日：2021-02-25

申请号：US16572568

申请日：2019-09-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Bo-Shiun Chen ,  Chun-Jen Chen ,  Chung-Ting Huang ,  Chi-Hsuan Tang ,  Jhong-Yi Huang ,  Guan-Ying Wu

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/15 ,  H01L29/66 ,  H01L21/02

Abstract: A transistor with strained superlattices as source/drain regions includes a substrate. A gate structure is disposed on the substrate. Two superlattices are respectively disposed at two sides of the gate structure and embedded in the substrate. The superlattices are strained. Each of the superlattices is formed by a repeated alternating stacked structure including a first epitaxial silicon germanium and a second epitaxial silicon germanium. The superlattices serve as source/drain regions of the transistor.

公开(公告)号：US12021134B2

公开(公告)日：2024-06-25

申请号：US18073539

申请日：2022-12-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chih Chuang ,  Chia-Jong Liu ,  Kuang-Hsiu Chen ,  Chung-Ting Huang ,  Chi-Hsuan Tang ,  Kai-Hsiang Wang ,  Bing-Yang Jiang ,  Yu-Lin Cheng ,  Chun-Jen Chen ,  Yu-Shu Lin ,  Jhong-Yi Huang ,  Chao-Nan Chen ,  Guan-Ying Wu

IPC: H01L29/66 ,  H01L29/423

CPC classification number: H01L29/6656 ,  H01L29/42364

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.