公开(公告)号：US11444151B2

公开(公告)日：2022-09-13

申请号：US17142268

申请日：2021-01-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Linggang Fang

IPC: H01L49/02 ,  H01L29/94 ,  H01L21/28

Abstract: A poly-insulator-poly (PIP) capacitor including a substrate having a capacitor forming region; a first capacitor dielectric layer on the capacitor forming region; a first poly electrode on the first capacitor dielectric layer; a second capacitor dielectric layer on the first poly electrode; and a second poly electrode on the second capacitor dielectric layer. A third poly electrode is disposed adjacent to a first sidewall of the second poly electrode. A third capacitor dielectric layer is disposed between the third poly electrode and the second poly electrode. A fourth poly electrode is disposed adjacent to a second sidewall of the second poly electrode opposite to the first sidewall. A fourth capacitor dielectric layer is disposed between the fourth poly electrode and the second poly electrode.

公开(公告)号：US12249647B2

公开(公告)日：2025-03-11

申请号：US17702831

申请日：2022-03-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chien Chang ,  Shen-De Wang ,  Cheng-Hua Yang ,  Linggang Fang ,  Jianjun Yang ,  Wei Ta

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

Abstract: A power device includes a substrate, an ion well in the substrate, a body region in the ion well, a source doped region in the body region, a drain doped region in the ion well, and gates on the substrate between the source doped region and the drain doped region. The gates include a first gate adjacent to the source doped region, a second gate adjacent to the drain doped region, and a stacked gate structure between the first gate and the second gate.

公开(公告)号：US10263000B2

公开(公告)日：2019-04-16

申请号：US15697459

申请日：2017-09-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Linggang Fang

IPC: H01L27/108 ,  H01L49/02

Abstract: A device including a capacitor includes an isolation structure, a first control gate, a first selective gate and a first dielectric layer. The isolation structure is disposed in a substrate. The first control gate and the first selective gate are disposed directly above the isolation structure. The first dielectric layer is vertically sandwiched by the first control gate and the first selective gate, thereby constituting the capacitor. The present invention also provides a method of forming the device including the capacitor.