公开(公告)号：US10332884B2

公开(公告)日：2019-06-25

申请号：US15802450

申请日：2017-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Che-Jung Hsu ,  Yu-Cheng Tung ,  Jianjun Yang ,  Yuan-Hsiang Chang ,  Chih-Chien Chang ,  Weichang Liu ,  Shen-De Wang ,  Kok Wun Tan

IPC: H01L27/092 ,  H01L27/11573 ,  H01L29/792 ,  H01L29/66 ,  H01L29/78

Abstract: A method of manufacturing FinFET semiconductor devices in memory regions and logic regions includes the steps of forming a first gate material layer on a substrate and fins, patterning the first gate material layer to form a control gate, forming a second gate material layer on the substrate and fins, performing an etch process to the cell region so that the second gate material layer in the cell region is lower than the second gate material layer in the peripheral region, patterning the second gate material layer to form a select gate in the cell region and a dummy gate in the logic region respectively.

公开(公告)号：US09666680B1

公开(公告)日：2017-05-30

申请号：US14944224

申请日：2015-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuan-Hsiang Chang ,  Shen-De Wang ,  Chih-Chien Chang ,  Jianjun Yang ,  Aaron Chen

IPC: H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/265 ,  H01L21/321 ,  H01L21/223 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/51 ,  H01L27/11521

CPC classification number: H01L29/42328 ,  H01L21/26586 ,  H01L21/28273 ,  H01L21/28562 ,  H01L21/31111 ,  H01L21/321 ,  H01L21/32133 ,  H01L27/11521 ,  H01L28/00 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/788

Abstract: A flash cell includes a gate and an erase gate. The gate is disposed on a substrate, wherein the gate includes a control gate on the substrate and a floating gate having a tip between the substrate and the control gate. The erase gate is disposed beside the gate, wherein the tip points toward the erase gate. The present invention also provides a flash cell forming process including the following steps. A gate is formed on a substrate, wherein the gate includes a floating gate on the substrate. An implantation process is performed on a side part of the floating gate, thereby forming a first doped region in the side part. At least a part of the first doped region is oxidized, thereby forming a floating gate having a tip.

公开(公告)号：US12249647B2

公开(公告)日：2025-03-11

申请号：US17702831

申请日：2022-03-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chien Chang ,  Shen-De Wang ,  Cheng-Hua Yang ,  Linggang Fang ,  Jianjun Yang ,  Wei Ta

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

Abstract: A power device includes a substrate, an ion well in the substrate, a body region in the ion well, a source doped region in the body region, a drain doped region in the ion well, and gates on the substrate between the source doped region and the drain doped region. The gates include a first gate adjacent to the source doped region, a second gate adjacent to the drain doped region, and a stacked gate structure between the first gate and the second gate.

公开(公告)号：US10651183B1

公开(公告)日：2020-05-12

申请号：US16221382

申请日：2018-12-14

Applicant: United Microelectronics Corp.

Inventor： Jianjun Yang ,  Cheng-Hua Yang ,  Fan-Chi Meng ,  Chih-Chien Chang ,  Shen-De Wang

IPC: H01L21/336 ,  H01L27/11517

Abstract: A manufacturing method of a semiconductor device includes: providing a substrate having memory and high voltage regions; sequentially forming a floating gate layer and a hard mask layer on the substrate; patterning the hard mask layer to form a first opening exposing a portion of the floating gate layer in the range of the memory region; patterning the hard mask layer and the floating gate layer to form a second opening overlapped with the high voltage region; performing a first thermal growth process to simultaneously form a first oxide structure on the portion of the floating gate layer exposed by the first opening, and to form a second oxide structure on a portion of the substrate overlapped with the second opening; removing the hard mask layer; and patterning the floating gate layer by using the first oxide structure as a mask.

公开(公告)号：US10020385B2

公开(公告)日：2018-07-10

申请号：US14220122

申请日：2014-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Shan Chiu ,  Shen-De Wang ,  Zhen Chen ,  Yuan-Hsiang Chang ,  Chih-Chien Chang ,  Jianjun Yang ,  Wei Ta

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L27/1157

CPC classification number: H01L29/66833 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/792

Abstract: The present invention provides a memory cell, which includes a substrate, a gate dielectric layer, a patterned material layer, a selection gate and a control gate. The gate dielectric layer is disposed on the substrate. The patterned material layer is disposed on the substrate, wherein the patterned material layer comprises a vertical portion and a horizontal portion. The selection gate is disposed on the gate dielectric layer and atone side of the vertical portion of the patterned material layer. The control gate is disposed on the horizontal portion of the patterned material layer and at another side of the vertical portion, wherein the vertical portion protrudes over a top of the selection gate. The present invention further provides another embodiment of a memory cell and manufacturing methods thereof.

公开(公告)号：US09583641B1

公开(公告)日：2017-02-28

申请号：US14960453

申请日：2015-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuan-Hsiang Chang ,  Yi-Shan Chiu ,  Chih-Chien Chang ,  Jianjun Yang ,  Wen-Chuan Chang

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7923 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66833

Abstract: A manufacturing method of a semiconductor device includes the following steps. A plurality of select gates are formed on a memory region of a semiconductor substrate. Two charge storage structures are formed between two adjacent select gates. A source region is formed in the semiconductor substrate, and the source region is formed between the two adjacent select gates. An insulation block is formed between the two charge storage structures and formed on the source region. A memory gate is formed on the insulation block, and the memory gate is connected to the two charge storage structures.

Abstract translation: 半导体器件的制造方法包括以下步骤。 多个选择栅极形成在半导体衬底的存储区域上。 在两个相邻的选择门之间形成两个电荷存储结构。 源区域形成在半导体衬底中，并且源区域形成在两个相邻的选择栅极之间。 在两个电荷存储结构之间形成绝缘块并形成在源极区上。 存储器栅极形成在绝缘块上，并且存储器栅极连接到两个电荷存储结构。

公开(公告)号：US10141194B1

公开(公告)日：2018-11-27

申请号：US15603465

申请日：2017-05-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi Qiang Mu ,  Chow Yee Lim ,  Hui Yang ,  Yong Bin Fan ,  Jianjun Yang ,  Chih-Chien Chang

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/28273 ,  H01L21/02071 ,  H01L21/02074 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first polysilicon layer is formed on a substrate. A planarization process to the first polysilicon layer is performed. A first etching back process to the first polysilicon layer is performed after the planarization process. A second etching back process to the first polysilicon layer is performed after the first etching back process. A first wet clean process to the first polysilicon layer is performed after the first etching back process and before the second etching back process.