公开(公告)号：US20240313074A1

公开(公告)日：2024-09-19

申请号：US18671941

申请日：2024-05-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wen Huang ,  Shih-An Huang

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/06 ,  H01L29/10 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42376 ,  H01L21/28088 ,  H01L21/28114 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/4966 ,  H01L29/66681 ,  H01L29/7816

Abstract: A work function metal gate device includes a gate, a drift region, a source, a drain and a first isolation structure. The gate includes a convex stair-shaped work function metal stack or a concave stair-shaped work function metal stack disposed on a substrate. The drift region is disposed in the substrate below a part of the gate. The source is located in the substrate and the drain is located in the drift region beside the gate. The first isolation structure is disposed in the drift region between the gate and the drain.

公开(公告)号：US20230014945A1

公开(公告)日：2023-01-19

申请号：US17945122

申请日：2022-09-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wen Huang ,  Shih-An Huang

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/49 ,  H01L21/28 ,  H01L29/10

Abstract: A work function metal gate device includes a gate, a drift region, a source, a drain and a first isolation structure. The gate includes a convex stair-shaped work function metal stack or a concave stair-shaped work function metal stack disposed on a substrate. The drift region is disposed in the substrate below a part of the gate. The source is located in the substrate and the drain is located in the drift region beside the gate. The first isolation structure is disposed in the drift region between the gate and the drain.

公开(公告)号：US20220149171A1

公开(公告)日：2022-05-12

申请号：US17128168

申请日：2020-12-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wen Huang ,  Shih-An Huang

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66

Abstract: A work function metal gate device includes a gate, a drift region, a source, a drain and a first isolation structure. The gate includes a convex stair-shaped work function metal stack or a concave stair-shaped work function metal stack disposed on a substrate. The drift region is disposed in the substrate below a part of the gate. The source is located in the substrate and the drain is located in the drift region beside the gate. The first isolation structure is disposed in the drift region between the gate and the drain.

公开(公告)号：US20240145564A1

公开(公告)日：2024-05-02

申请号：US17994007

申请日：2022-11-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tzu-I Tsai ,  Shih-An Huang

IPC: H01L29/423 ,  H01L29/40

CPC classification number: H01L29/42364 ,  H01L29/401

Abstract: The invention provides a semiconductor structure, which comprises a substrate, a gate dielectric layer on the substrate, wherein the gate dielectric layer comprises two sidewall portions and a horizontal portion between the two sidewall portions, wherein a height of the horizontal portion is lower than that of the two sidewall portions, and the horizontal portion and the two sidewall portions are perpendicular to each other, and a gate conductive layer on the horizontal portion of the gate dielectric layer.

公开(公告)号：US11482605B2

公开(公告)日：2022-10-25

申请号：US17128168

申请日：2020-12-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wen Huang ,  Shih-An Huang

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/113 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/49 ,  H01L21/28 ,  H01L29/10

Abstract: A work function metal gate device includes a gate, a drift region, a source, a drain and a first isolation structure. The gate includes a convex stair-shaped work function metal stack or a concave stair-shaped work function metal stack disposed on a substrate. The drift region is disposed in the substrate below a part of the gate. The source is located in the substrate and the drain is located in the drift region beside the gate. The first isolation structure is disposed in the drift region between the gate and the drain.

公开(公告)号：US12021129B2

公开(公告)日：2024-06-25

申请号：US17945122

申请日：2022-09-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wen Huang ,  Shih-An Huang

IPC: H01L29/76 ,  H01L21/28 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/94 ,  H01L31/113

CPC classification number: H01L29/42376 ,  H01L21/28088 ,  H01L21/28114 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/4966 ,  H01L29/66681 ,  H01L29/7816

Abstract: A work function metal gate device includes a gate, a drift region, a source, a drain and a first isolation structure. The gate includes a convex stair-shaped work function metal stack or a concave stair-shaped work function metal stack disposed on a substrate. The drift region is disposed in the substrate below a part of the gate. The source is located in the substrate and the drain is located in the drift region beside the gate. The first isolation structure is disposed in the drift region between the gate and the drain.

公开(公告)号：US09502260B2

公开(公告)日：2016-11-22

申请号：US14599559

申请日：2015-01-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-An Huang ,  Kun-Hsien Lee

IPC: H01L21/308 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/3081 ,  H01L21/3086 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: The present invention provides a method for forming a semiconductor structure, including: firstly, providing a substrate, a fin structure being disposed on the substrate, a gate structure crossing over the fin structure, and a first hard mask being disposed on the top surface of the gate structure. Next, a dielectric layer is formed, covering the substrate, the fin structure and the gate structure. Afterwards, a second hard mask is formed on the top surface of the first hard mask, where the width of the second hard mask is larger than the width of the first hard mask, a bottom surface of the second hard mask and a top surface of the first hard mask are on the same level. An etching process is then performed to remove parts of the dielectric and parts of the fin structure.

Abstract translation: 本发明提供了一种形成半导体结构的方法，包括：首先，提供基板，翅片结构设置在基板上，栅极结构与翅片结构交叉，第一硬掩模设置在第一硬掩模的顶表面上 门结构。 接下来，形成介电层，覆盖基板，翅片结构和栅极结构。 之后，在第一硬掩模的顶表面上形成第二硬掩模，其中第二硬掩模的宽度大于第一硬掩模的宽度，第二硬掩模的底面和第二硬掩模的顶表面 第一个硬面罩在同一水平上。 然后进行蚀刻处理以去除电介质的一部分和鳍结构的一部分。

公开(公告)号：US20160189970A1

公开(公告)日：2016-06-30

申请号：US14599559

申请日：2015-01-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-An Huang ,  Kun-Hsien Lee

IPC: H01L21/308 ,  H01L29/78

CPC classification number: H01L21/3081 ,  H01L21/3086 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: The present invention provides a method for forming a semiconductor structure, including: firstly, providing a substrate, a fin structure being disposed on the substrate, a gate structure crossing over the fin structure, and a first hard mask being disposed on the top surface of the gate structure. Next, a dielectric layer is formed, covering the substrate, the fin structure and the gate structure. Afterwards, a second hard mask is formed on the top surface of the first hard mask, where the width of the second hard mask is larger than the width of the first hard mask, a bottom surface of the second hard mask and a top surface of the first hard mask are on the same level. An etching process is then performed to remove parts of the dielectric and parts of the fin structure.

Abstract translation: 本发明提供了一种形成半导体结构的方法，包括：首先，提供基板，翅片结构设置在基板上，栅极结构与翅片结构交叉，第一硬掩模设置在第一硬掩模的顶表面上 门结构。 接下来，形成介电层，覆盖基板，翅片结构和栅极结构。 之后，在第一硬掩模的顶表面上形成第二硬掩模，其中第二硬掩模的宽度大于第一硬掩模的宽度，第二硬掩模的底面和第二硬掩模的顶表面 第一个硬面罩在同一水平上。 然后进行蚀刻处理以去除电介质的一部分和鳍结构的一部分。