公开(公告)号：US20220293624A1

公开(公告)日：2022-09-15

申请号：US17224100

申请日：2021-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  ZHIGUO LI ,  CHI REN

IPC: H01L27/11578 ,  H01L29/66 ,  H01L27/11551 ,  H01L29/78

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell for FinFET includes a fin, a control gate and a selective metal gate. The fin is on a top surface of a substrate, wherein the fin has two sidewalls and a top surface, and the fin includes a memory region and a logic region. The control gate is disposed over the fin of the memory region and covers the two sidewalls and the top surface of the fin, wherein the control gate includes a charge trapping layer and a control electrode, wherein the charge trapping layer is sandwiched by the fin and the control electrode. The selective metal gate is disposed over the fin adjacent to the control gate and covers the two sidewalls and the top surface of the fin. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

公开(公告)号：US20230299160A1

公开(公告)日：2023-09-21

申请号：US18199967

申请日：2023-05-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  ZHIGUO LI ,  Xiaojuan Gao ,  CHI REN

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

CPC classification number: H01L29/42328 ,  H01L29/66825 ,  H01L29/40114 ,  H01L29/7883

Abstract: A method for forming a semiconductor memory device is disclosed. A substrate is provided. A source diffusion region is formed in the substrate. Two floating gates are on opposite sides of the source diffusion region. A first dielectric cap layer is formed directly on each of the floating gates. An erase gate is formed on the source diffusion region. The erase gate partially overlaps an upper inner corner of each of the floating gates. A second dielectric cap layer is formed on the erase gate and the first dielectric cap layer. A select gate is formed on a sidewall of the first dielectric cap layer in a self-aligned manner. A drain diffusion region is formed in the substrate and adjacent to the select gate.

公开(公告)号：US20220352195A1

公开(公告)日：2022-11-03

申请号：US17864435

申请日：2022-07-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  ZHIGUO LI ,  CHI REN

IPC: H01L27/11578 ,  H01L29/66 ,  H01L27/11551 ,  H01L29/78

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell for FinFET includes a fin, a control gate and a selective metal gate. The fin is on a top surface of a substrate, wherein the fin has two sidewalls and a top surface, and the fin includes a memory region and a logic region. The control gate is disposed over the fin of the memory region and covers the two sidewalls and the top surface of the fin, wherein the control gate includes a charge trapping layer and a control electrode, wherein the charge trapping layer is sandwiched by the fin and the control electrode. The selective metal gate is disposed over the fin adjacent to the control gate and covers the two sidewalls and the top surface of the fin. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

公开(公告)号：US20230029468A1

公开(公告)日：2023-02-02

申请号：US17510371

申请日：2021-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  ZHIGUO LI ,  Xiaojuan Gao ,  CHI REN

IPC: H01L29/423 ,  H01L29/788 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor memory device includes a substrate; a source diffusion region in the substrate; a pair of floating gates disposed on opposite of the source diffusion region; a first dielectric cap layer disposed directly on each of the floating gates; an erase gate disposed on the source diffusion region and partially overlapping an upper inner corner of each of the floating gates; a second dielectric cap layer disposed on the erase gate and the first dielectric cap layer; a select gate disposed on a sidewall of the first dielectric cap layer; and a drain diffusion region disposed in the substrate and adjacent to the select gate.

公开(公告)号：US20150115346A1

公开(公告)日：2015-04-30

申请号：US14062905

申请日：2013-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Yuan Hsu ,  ZHIGUO LI ,  CHI REN

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/11521 ,  H01L29/42324 ,  H01L29/66825

Abstract: A semiconductor memory device includes a substrate, shallow trench isolations protruding from the substrate, a floating gate formed conformally on the surface of the recess between each shallow trench isolation, a tunnel layer formed between each floating gate and the substrate, a dielectric layer formed conformally on the floating gates, and a control gate formed on the dielectric layer.

Abstract translation: 半导体存储器件包括衬底，从衬底突出的浅沟槽隔离物，在每个浅沟槽隔离件之间的凹槽表面上共形形成的浮栅，在每个浮置栅极和衬底之间形成的隧道层，保形地形成的电介质层 在浮置栅极上，以及形成在电介质层上的控制栅极。