公开(公告)号：US20230299160A1

公开(公告)日：2023-09-21

申请号：US18199967

申请日：2023-05-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  ZHIGUO LI ,  Xiaojuan Gao ,  CHI REN

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

CPC classification number: H01L29/42328 ,  H01L29/66825 ,  H01L29/40114 ,  H01L29/7883

Abstract: A method for forming a semiconductor memory device is disclosed. A substrate is provided. A source diffusion region is formed in the substrate. Two floating gates are on opposite sides of the source diffusion region. A first dielectric cap layer is formed directly on each of the floating gates. An erase gate is formed on the source diffusion region. The erase gate partially overlaps an upper inner corner of each of the floating gates. A second dielectric cap layer is formed on the erase gate and the first dielectric cap layer. A select gate is formed on a sidewall of the first dielectric cap layer in a self-aligned manner. A drain diffusion region is formed in the substrate and adjacent to the select gate.

公开(公告)号：US20220352195A1

公开(公告)日：2022-11-03

申请号：US17864435

申请日：2022-07-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  ZHIGUO LI ,  CHI REN

IPC: H01L27/11578 ,  H01L29/66 ,  H01L27/11551 ,  H01L29/78

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell for FinFET includes a fin, a control gate and a selective metal gate. The fin is on a top surface of a substrate, wherein the fin has two sidewalls and a top surface, and the fin includes a memory region and a logic region. The control gate is disposed over the fin of the memory region and covers the two sidewalls and the top surface of the fin, wherein the control gate includes a charge trapping layer and a control electrode, wherein the charge trapping layer is sandwiched by the fin and the control electrode. The selective metal gate is disposed over the fin adjacent to the control gate and covers the two sidewalls and the top surface of the fin. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

公开(公告)号：US20230402517A1

公开(公告)日：2023-12-14

申请号：US17835965

申请日：2022-06-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  CHI REN

IPC: H01L29/423 ,  H01L29/788 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/42328 ,  H01L29/7883 ,  H01L29/40114 ,  H01L29/66825

Abstract: A semiconductor memory device includes a substrate, a pair of floating gates disposed on the substrate, a source line doped region in the substrate between the floating gates, an erase gate disposed between the floating gates and on the source line doped region, a word line disposed on the substrate and adjacent to a side of each of the floating gates opposite to the erase gate, and a bit line doped region in the substrate and adjacent to the word line. An upper surface of the source line doped region has a concave profile lower than a surface of the substrate and with a radius between 40 nm and 60 nm in a cross-sectional view perpendicular to the floating gates.

公开(公告)号：US20230039408A1

公开(公告)日：2023-02-09

申请号：US17472586

申请日：2021-09-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Sung Huang ,  CHI REN

IPC: H01L29/792 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor memory device includes a substrate; a control gate disposed on the substrate; a source diffusion region disposed in the substrate and on a first side of the control gate; a select gate disposed on the source diffusion region, wherein the select gate has a recessed top surface; a charge storage structure disposed under the control gate; a first spacer disposed between the select gate and the control gate and between the charge storage structure and the select gate; a wordline gate disposed on a second side of the control gate opposite to the select gate; a second spacer between the wordline gate and the control gate; and a drain diffusion region disposed in the substrate and adjacent to the wordline gate.

公开(公告)号：US20140183614A1

公开(公告)日：2014-07-03

申请号：US13733147

申请日：2013-01-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHAOBING LI ,  Cheng-Yuan Hsu ,  CHI REN

IPC: H01L29/788

CPC classification number: H01L29/42324 ,  H01L21/76224 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7881

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, at least a first gate, a shallow trench isolation (STI) and a third gate. The first gate is disposed on the semiconductor substrate, and the first gate partially overlaps the third gate and the shallow trench isolation. Furthermore, the third gate is disposed in a shallow trench isolation, and the third gate includes at least a protrusion.

Abstract translation: 提供半导体器件。 半导体器件包括半导体衬底，至少第一栅极，浅沟槽隔离（STI）和第三栅极。 第一栅极设置在半导体衬底上，第一栅极部分地与第三栅极重叠并且浅沟槽隔离。 此外，第三栅极设置在浅沟槽隔离中，并且第三栅极至少包括突起。

公开(公告)号：US20240332384A1

公开(公告)日：2024-10-03

申请号：US18739341

申请日：2024-06-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  CHI REN

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L29/42328 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7883

Abstract: A semiconductor memory device includes a substrate, an active region defined in the substrate by a trench isolation structure, a pair of floating gates on the substrate and at two sides of a fish-bone shaped recessed region of the active region, a source line doped region in the fish-bone shaped recessed region of the active region, wherein a bottom surface of the source line doped region extends above a bottom surface of the trench isolation structure, an erase gate disposed between the floating gates and on the source line doped region, a word line disposed on the substrate and adjacent to a side of each of the floating gates opposite to the erase gate, and a bit line doped region in the substrate and adjacent to the word line.

公开(公告)号：US20220293624A1

公开(公告)日：2022-09-15

申请号：US17224100

申请日：2021-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  ZHIGUO LI ,  CHI REN

IPC: H01L27/11578 ,  H01L29/66 ,  H01L27/11551 ,  H01L29/78

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell for FinFET includes a fin, a control gate and a selective metal gate. The fin is on a top surface of a substrate, wherein the fin has two sidewalls and a top surface, and the fin includes a memory region and a logic region. The control gate is disposed over the fin of the memory region and covers the two sidewalls and the top surface of the fin, wherein the control gate includes a charge trapping layer and a control electrode, wherein the charge trapping layer is sandwiched by the fin and the control electrode. The selective metal gate is disposed over the fin adjacent to the control gate and covers the two sidewalls and the top surface of the fin. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

公开(公告)号：US20200135274A1

公开(公告)日：2020-04-30

申请号：US16173406

申请日：2018-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： LIANG YI ,  ZHAOBING LI ,  CHI REN

IPC: G11C16/04 ,  H01L27/11517 ,  G11C13/00 ,  H01L45/00

Abstract: A structure of nonvolatile memory device includes a substrate, having a logic device region and a memory cell region. A first gate structure for a low-voltage transistor is disposed over the substrate in the logic device region, wherein the first gate structure comprises a single-layer polysilicon. A second gate structure for a memory cell is disposed over the substrate in the memory cell region. The second gate structure includes a gate insulating layer on the substrate. A floating gate layer is disposed on the gate insulating layer, wherein the floating gate layer comprises a first polysilicon layer and a second polysilicon layer as a stacked structure. A memory dielectric layer is disposed on the floating gate layer. A control gate layer is disposed on the memory dielectric layer, wherein the control gate layer and the single-layer polysilicon are originated from a preliminary polysilicon layer in same.

公开(公告)号：US20240194797A1

公开(公告)日：2024-06-13

申请号：US18444785

申请日：2024-02-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Sung Huang ,  CHI REN

IPC: H01L29/792 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66833

Abstract: Abstract of Disclosure A control gate is formed on the substrate. A source diffusion region is formed in the substrate and on a first side of the control gate. A select gate is formed on the source diffusion region. The select gate has a recessed top surface. A charge storage structure is formed under the control gate. A first spacer is formed between the select gate and the control gate and between the charge storage structure and the select gate. A wordline gate is formed on a second side of the control gate opposite to the select gate. A second spacer is formed between the wordline gate and the control gate. A drain diffusion region is formed in the substrate and adjacent to the wordline gate.

公开(公告)号：US20230128356A1

公开(公告)日：2023-04-27

申请号：US17527182

申请日：2021-11-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Aaron Chen ,  CHI REN ,  Chao-Sheng Hsieh

IPC: H01L27/11521 ,  H01L27/11558

Abstract: An electrically erasable programmable read only memory (EEPROM) cell includes a first gate, a second gate and an erasing gate. The first gate and the second gate are disposed on a substrate, wherein the first gate includes a first floating gate and a first control gate stacked from bottom to top, and the second gate includes a second floating gate and a second control gate stacked from bottom to top. The erasing gate is sandwiched by the first gate and the second gate, wherein a side part of the first floating gate and a side part of the second floating gate right below the erasing gate both have multiple tips. The present invention also provides a method of forming said electrically erasable programmable read only memory (EEPROM) cell.