公开(公告)号：US11366604B1

公开(公告)日：2022-06-21

申请号：US17210545

申请日：2021-03-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ko-Chin Chang ,  Ming-Jen Chang ,  Cheng-Hsiao Lai ,  Yu-Syuan Lin ,  Chi-Fa Lien ,  Ying-Ting Lin ,  Yung-Tsai Hsu

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/28 ,  G11C16/22

Abstract: A physically unclonable function includes a flash memory, a current comparator and a controller. The flash memory includes a plurality of memory cells. A method of operating the physically unclonable function circuit includes the controller setting the plurality of memory cells to an initial data state, the controller setting the plurality of memory cells between the initial data state and an adjacent data state of the initial data state, the current comparator reading a first current from a memory cell in a first section of the plurality of the memory cells, the current comparator reading a second current from a memory cell in a second section of the plurality of the memory cells, and the current comparator outputting a random bit according to the first current and the second current.

公开(公告)号：US12237027B2

公开(公告)日：2025-02-25

申请号：US17966881

申请日：2022-10-16

Applicant: United Microelectronics Corp.

Inventor： Chung-Hao Chen ,  Chi-Hsiu Hsu ,  Chi-Fa Lien ,  Ying-Ting Lin ,  Cheng-Hsiao Lai ,  Ya-Nan Mou

IPC: G11C17/16 ,  G11C16/04 ,  G11C16/24

Abstract: Provided is an anti-fuse memory including a anti-fuse memory cell including an isolation structure, a select gate, first and second gate insulating layers, an anti-fuse gate, and first, second and third doped regions. The isolation structure is disposed in a substrate. The select gate is disposed on the substrate. The first gate insulating layer is disposed between the select gate and the substrate. The anti-fuse gate is disposed on the substrate and partially overlapped with the isolation structure. The second gate insulating layer is disposed between the anti-fuse gate and the substrate. The first doped region and the second doped region are disposed in the substrate at opposite sides of the select gate, respectively, wherein the first doped region is located between the select gate and the anti-fuse gate. The third doped region is disposed in the substrate and located between the first doped region and the isolation structure.

公开(公告)号：US20240071535A1

公开(公告)日：2024-02-29

申请号：US17966881

申请日：2022-10-16

Applicant: United Microelectronics Corp.

Inventor： Chung-Hao Chen ,  Chi-Hsiu Hsu ,  Chi-Fa Lien ,  Ying-Ting Lin ,  Cheng-Hsiao Lai ,  Ya-Nan Mou

IPC: G11C17/16 ,  G11C16/04 ,  G11C16/24

CPC classification number: G11C17/16 ,  G11C16/0433 ,  G11C16/24

Abstract: Provided is an anti-fuse memory including a anti-fuse memory cell including an isolation structure, a select gate, first and second gate insulating layers, an anti-fuse gate, and first, second and third doped regions. The isolation structure is disposed in a substrate. The select gate is disposed on the substrate. The first gate insulating layer is disposed between the select gate and the substrate. The anti-fuse gate is disposed on the substrate and partially overlapped with the isolation structure. The second gate insulating layer is disposed between the anti-fuse gate and the substrate. The first doped region and the second doped region are disposed in the substrate at opposite sides of the select gate, respectively, wherein the first doped region is located between the select gate and the anti-fuse gate. The third doped region is disposed in the substrate and located between the first doped region and the isolation structure.