公开(公告)号：US11366604B1

公开(公告)日：2022-06-21

申请号：US17210545

申请日：2021-03-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ko-Chin Chang ,  Ming-Jen Chang ,  Cheng-Hsiao Lai ,  Yu-Syuan Lin ,  Chi-Fa Lien ,  Ying-Ting Lin ,  Yung-Tsai Hsu

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/28 ,  G11C16/22

Abstract: A physically unclonable function includes a flash memory, a current comparator and a controller. The flash memory includes a plurality of memory cells. A method of operating the physically unclonable function circuit includes the controller setting the plurality of memory cells to an initial data state, the controller setting the plurality of memory cells between the initial data state and an adjacent data state of the initial data state, the current comparator reading a first current from a memory cell in a first section of the plurality of the memory cells, the current comparator reading a second current from a memory cell in a second section of the plurality of the memory cells, and the current comparator outputting a random bit according to the first current and the second current.

公开(公告)号：US12237027B2

公开(公告)日：2025-02-25

申请号：US17966881

申请日：2022-10-16

Applicant: United Microelectronics Corp.

Inventor： Chung-Hao Chen ,  Chi-Hsiu Hsu ,  Chi-Fa Lien ,  Ying-Ting Lin ,  Cheng-Hsiao Lai ,  Ya-Nan Mou

IPC: G11C17/16 ,  G11C16/04 ,  G11C16/24

Abstract: Provided is an anti-fuse memory including a anti-fuse memory cell including an isolation structure, a select gate, first and second gate insulating layers, an anti-fuse gate, and first, second and third doped regions. The isolation structure is disposed in a substrate. The select gate is disposed on the substrate. The first gate insulating layer is disposed between the select gate and the substrate. The anti-fuse gate is disposed on the substrate and partially overlapped with the isolation structure. The second gate insulating layer is disposed between the anti-fuse gate and the substrate. The first doped region and the second doped region are disposed in the substrate at opposite sides of the select gate, respectively, wherein the first doped region is located between the select gate and the anti-fuse gate. The third doped region is disposed in the substrate and located between the first doped region and the isolation structure.

公开(公告)号：US11823746B2

公开(公告)日：2023-11-21

申请号：US17673829

申请日：2022-02-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shan Ho ,  Ying-Ting Lin ,  Chung-Yi Luo ,  Kuo-Cheng Chou ,  Cheng-Hsiao Lai ,  Ming-Jen Chang ,  Yung-Tsai Hsu ,  Cheng-Chieh Cheng

IPC: G11C16/28 ,  G11C16/24 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/28 ,  G11C16/08 ,  G11C16/102 ,  G11C16/24

Abstract: A memory sector with trimmed reference currents, including eight unit cells corresponding to an even word line and eight unit cells corresponding to an odd word line, and each unit cell has erased state and programmed state, wherein the logic state of unit cell corresponding to the odd word line is determined by a first reference current based on cell currents of the 8 unit cells corresponding to the even word line in programmed state and cell currents of the eight unit cells corresponding to the odd word line in erased state, and the logic state of unit cell corresponding to the even word line is determined by a second reference current based on cell currents of the eight unit cells corresponding to the even word line in erased state and cell currents of the 8 unit cells corresponding to the odd word line in programmed state.

公开(公告)号：US20230223091A1

公开(公告)日：2023-07-13

申请号：US17673829

申请日：2022-02-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shan Ho ,  Ying-Ting Lin ,  Chung-Yi Luo ,  Kuo-Cheng Chou ,  Cheng-Hsiao Lai ,  Ming-Jen Chang ,  Yung-Tsai Hsu ,  Cheng-Chieh Cheng

IPC: G11C16/28 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24

CPC classification number: G11C16/28 ,  G11C16/102 ,  G11C16/08 ,  G11C16/24

Abstract: A memory sector with trimmed reference currents, including eight unit cells corresponding to an even word line and eight unit cells corresponding to an odd word line, and each unit cell has erased state and programmed state, wherein the logic state of unit cell corresponding to the odd word line is determined by a first reference current based on cell currents of the 8 unit cells corresponding to the even word line in programmed state and cell currents of the eight unit cells corresponding to the odd word line in erased state, and the logic state of unit cell corresponding to the even word line is determined by a second reference current based on cell currents of the eight unit cells corresponding to the even word line in erased state and cell currents of the 8 unit cells corresponding to the odd word line in programmed state.

公开(公告)号：US20240071535A1

公开(公告)日：2024-02-29

申请号：US17966881

申请日：2022-10-16

Applicant: United Microelectronics Corp.

Inventor： Chung-Hao Chen ,  Chi-Hsiu Hsu ,  Chi-Fa Lien ,  Ying-Ting Lin ,  Cheng-Hsiao Lai ,  Ya-Nan Mou

IPC: G11C17/16 ,  G11C16/04 ,  G11C16/24

CPC classification number: G11C17/16 ,  G11C16/0433 ,  G11C16/24

Abstract: Provided is an anti-fuse memory including a anti-fuse memory cell including an isolation structure, a select gate, first and second gate insulating layers, an anti-fuse gate, and first, second and third doped regions. The isolation structure is disposed in a substrate. The select gate is disposed on the substrate. The first gate insulating layer is disposed between the select gate and the substrate. The anti-fuse gate is disposed on the substrate and partially overlapped with the isolation structure. The second gate insulating layer is disposed between the anti-fuse gate and the substrate. The first doped region and the second doped region are disposed in the substrate at opposite sides of the select gate, respectively, wherein the first doped region is located between the select gate and the anti-fuse gate. The third doped region is disposed in the substrate and located between the first doped region and the isolation structure.

公开(公告)号：US20180292848A1

公开(公告)日：2018-10-11

申请号：US15607266

申请日：2017-05-26

Applicant: United Microelectronics Corp.

Inventor： Chai-Wei Fu ,  Cheng-Hsiao Lai ,  Ying-Ting Lin ,  Yuan-Hui Chen ,  Ya-Nan Mou ,  Yung-Hsiang Lin ,  Hsueh-Chen Cheng

IPC: G05F1/44 ,  G05F1/46 ,  G05F1/575 ,  G05F1/56

Abstract: A voltage regulating circuit provides a feedback voltage and an output voltage based on a power voltage. The voltage regulating circuit includes a reference voltage generator and a compensating circuit. The reference voltage generator receives the power voltage, produces the feedback voltage, and includes an impedance having first and second terminals. The second terminal is coupled to a ground voltage and a first current flows through the impedance at the first terminal to produce the feedback voltage. The compensating circuit includes a negative threshold voltage (NVT) transistor having a source terminal, a drain terminal and a gate terminal. The source terminal receives a power voltage, the drain terminal is connected to the gate terminal and coupled to the first terminal of the impedance through a path to add a second current to the first current when the NVT transistor is turned on under an operational condition at the FF corner.

公开(公告)号：US10095251B1

公开(公告)日：2018-10-09

申请号：US15607266

申请日：2017-05-26

Applicant: United Microelectronics Corp.

Inventor： Chai-Wei Fu ,  Cheng-Hsiao Lai ,  Ying-Ting Lin ,  Yuan-Hui Chen ,  Ya-Nan Mou ,  Yung-Hsiang Lin ,  Hsueh-Chen Cheng

IPC: G05F1/44 ,  G05F1/46 ,  G05F1/575 ,  G05F1/56

Abstract: A voltage regulating circuit provides a feedback voltage and an output voltage based on a power voltage. The voltage regulating circuit includes a reference voltage generator and a compensating circuit. The reference voltage generator receives the power voltage, produces the feedback voltage, and includes an impedance having first and second terminals. The second terminal is coupled to a ground voltage and a first current flows through the impedance at the first terminal to produce the feedback voltage. The compensating circuit includes a negative threshold voltage (NVT) transistor having a source terminal, a drain terminal and a gate terminal. The source terminal receives a power voltage, the drain terminal is connected to the gate terminal and coupled to the first terminal of the impedance through a path to add a second current to the first current when the NVT transistor is turned on under an operational condition at the FF corner.