公开(公告)号：US20240347459A1

公开(公告)日：2024-10-17

申请号：US18317117

申请日：2023-05-15

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou ,  Ding Lung Chen

IPC: H01L23/528

CPC classification number: H01L23/5286

Abstract: Provided is a semiconductor including a substrate, a semiconductor element disposed on the substrate, an interconnect structure, first and second power deliver lines, and first and second power deliver network (PDN) structures. The interconnect structure is disposed in the element region, above the semiconductor element, and electrically connected with the semiconductor element. The first and the second power deliver lines are disposed above the interconnect structure and electrically connected to the first and the second power supplies, respectively. The first PDN structure is disposed between the substrate and the first power deliver line, and connected to the first power deliver line and a lowest circuit layer of the interconnect structure. The second PDN structure is disposed between the substrate and the second power deliver line, and connected to the second power deliver line and the lowest circuit layer of the interconnect structure.

公开(公告)号：US12159917B2

公开(公告)日：2024-12-03

申请号：US17320071

申请日：2021-05-13

Applicant: United Microelectronics Corp.

Inventor： Xiang Li ,  Ding Lung Chen ,  Changda Yao

IPC: H01L29/66 ,  H01L27/06

Abstract: A method of manufacturing a capacitor structure is provided, including the following steps. A substrate is provided. A first doped silicon material layer is formed on the substrate. A surface flattening process is performed on the first doped silicon material layer through a plasma treatment. An insulating material layer is formed on the first doped silicon material layer after the surface flattening process is performed. A second doped silicon material layer is formed on the insulating material layer. The first doped silicon material layer is patterned into a first electrode. The insulating material layer is patterned into an insulating layer. The second doped silicon material layer is patterned into a second electrode. The method of manufacturing the capacitor structure may be used to produce a capacitor with better reliability and may improve capacitance density.

公开(公告)号：US20220344492A1

公开(公告)日：2022-10-27

申请号：US17320071

申请日：2021-05-13

Applicant: United Microelectronics Corp.

Inventor： Xiang Li ,  Ding Lung Chen ,  Changda Yao

IPC: H01L29/66

Abstract: A method of manufacturing a capacitor structure is provided, including the following steps. A substrate is provided. A first doped silicon material layer is formed on the substrate. A surface flattening process is performed on the first doped silicon material layer through a plasma treatment. An insulating material layer is formed on the first doped silicon material layer after the surface flattening process is performed. A second doped silicon material layer is formed on the insulating material layer. The first doped silicon material layer is patterned into a first electrode. The insulating material layer is patterned into an insulating layer. The second doped silicon material layer is patterned into a second electrode. The method of manufacturing the capacitor structure may be used to produce a capacitor with better reliability and may improve capacitance density.