公开(公告)号：US11664372B2

公开(公告)日：2023-05-30

申请号：US16262779

申请日：2019-01-30

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou

IPC: H01L27/06 ,  H01L27/12 ,  H01L21/768 ,  H01L23/522 ,  H01L21/762 ,  H01L23/528

CPC classification number: H01L27/0688 ,  H01L21/76251 ,  H01L21/76898 ,  H01L23/528 ,  H01L23/5226 ,  H01L27/1203

Abstract: A semiconductor device is provided, including a buried oxide layer, having a first side and a second side. A silicon-based device layer is disposed on the first side of the buried oxide layer. The silicon-based device layer includes a first interconnection structure. A semiconductor-based device layer is disposed on the second side of the buried oxide layer. The semiconductor-based device layer includes a second interconnection structure.

公开(公告)号：US20220181199A1

公开(公告)日：2022-06-09

申请号：US17679133

申请日：2022-02-24

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou

IPC: H01L21/768 ,  H01L27/12 ,  H01L23/522

Abstract: A semiconductor device is provided. The semiconductor device includes a device substrate, having a device structure layer and a buried dielectric layer, wherein the buried dielectric layer is disposed on a semiconductor layer of the device structure layer and the device substrate comprises a device structure. A metal layer is disposed on the buried dielectric layer and surrounded by a first inter-layer dielectric (ILD) layer. A region of the metal layer has a plurality of openings. The buried dielectric layer has an air gap under and exposing the region of the metal layer with the openings, wherein the air gap is located above the device structure in the device substrate. A second ILD layer is disposed on the metal layer and sealing the air gap at the openings of the metal layer.

公开(公告)号：US10354580B2

公开(公告)日：2019-07-16

申请号：US15698221

申请日：2017-09-07

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou

IPC: H01L25/16 ,  H01L33/62 ,  H01L25/075 ,  G09G3/32 ,  H03K17/041 ,  H01L21/8238

Abstract: An integrated LED display is provided. The integrated LED display includes a complementary metal-oxide-semiconductor (CMOS) wafer including a driver circuitry fabricated on a substrate. Further, an insulating layer is disposed over the CMOS wafer. A conductive semiconductor layer is disposed on the insulating layer. A LED array is disposed on the conductive semiconductor layer and the LED array connected to the driver circuitry. The LED array includes a photo device array, disposed on the conductive semiconductor layer, and a switch device array, disposed on the conductive semiconductor layer.

公开(公告)号：US20190073943A1

公开(公告)日：2019-03-07

申请号：US15698221

申请日：2017-09-07

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou

IPC: G09G3/32 ,  H01L21/8238 ,  H01L25/16 ,  H03K17/041 ,  H01L25/075 ,  H01L33/62

CPC classification number: G09G3/32 ,  G09G2300/08 ,  H01L21/8238 ,  H01L25/0753 ,  H01L25/167 ,  H01L27/15 ,  H01L27/156 ,  H01L33/62 ,  H03K17/04106

Abstract: An integrated LED display is provided. The integrated LED display includes a complementary metal-oxide-semiconductor (CMOS) wafer including a driver circuitry fabricated on a substrate. Further, an insulating layer is disposed over the CMOS wafer. A conductive semiconductor layer is disposed on the insulating layer. A LED array is disposed on the conductive semiconductor layer and the LED array connected to the driver circuitry. The LED array includes a photo device array, disposed on the conductive semiconductor layer, and a switch device array, disposed on the conductive semiconductor layer.

公开(公告)号：US11758815B2

公开(公告)日：2023-09-12

申请号：US17022150

申请日：2020-09-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Biao Zhou

IPC: H10N30/05 ,  H10N30/072 ,  H10N30/80

CPC classification number: H10N30/05 ,  H10N30/072 ,  H10N30/80

Abstract: A semiconductor module and a method for manufacturing the same are provided. The semiconductor module includes a substrate comprising a front side and at least one semiconductor device formed on the front side, a shielding structure formed on the at least one semiconductor device, and a piezoelectric layer formed on the shielding structure.

公开(公告)号：US20220208852A1

公开(公告)日：2022-06-30

申请号：US17156967

申请日：2021-01-25

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou

IPC: H01L27/20 ,  H01L29/16 ,  H01L29/78 ,  H01L29/20 ,  H01L29/778 ,  H01L21/8258 ,  H01L23/34 ,  H01L23/367 ,  H01L23/552 ,  H03H9/17 ,  H03H9/54 ,  H03H9/56 ,  H03H3/02

Abstract: A structure of a semiconductor device is provided, including a circuit substrate. A first metal bulk layer is disposed on the circuit substrate. A buffer layer is disposed on the first metal bulk layer. An absorbing layer is disposed on the buffer layer. A first electrode layer is disposed on the absorbing layer. A plurality of piezoelectric material units are disposed on the first electrode layer. A protection layer is conformally disposed on the piezoelectric material units. A second metal bulk layer is disposed over the piezoelectric material units, and including a first part and a second part. The first part penetrating through the protection layer is disposed on the piezoelectric material units, serving as a second electrode layer. The second part is at a same level of the first part, and at least electrically connecting to the first electrode layer.

公开(公告)号：US20200243515A1

公开(公告)日：2020-07-30

申请号：US16262779

申请日：2019-01-30

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou

IPC: H01L27/06 ,  H01L27/12 ,  H01L23/528 ,  H01L23/522 ,  H01L21/762 ,  H01L21/768

Abstract: A semiconductor device is provided, including a buried oxide layer, having a first side and a second side. A silicon-based device layer is disposed on the first side of the buried oxide layer. The silicon-based device layer includes a first interconnection structure. A semiconductor-based device layer is disposed on the second side of the buried oxide layer. The semiconductor-based device layer includes a second interconnection structure.

公开(公告)号：US10566418B2

公开(公告)日：2020-02-18

申请号：US16152240

申请日：2018-10-04

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/84 ,  H01L49/02 ,  H01L23/535 ,  H01L21/762 ,  H01L27/12 ,  H01L21/3105

Abstract: A semiconductor device is provided. The semiconductor device includes an insulating structure and a dielectric structure. The insulating structure is disposed on a substrate and has a plurality of openings. The dielectric structure is disposed on the insulating structure and extending into the plurality of openings.

公开(公告)号：US09620649B1

公开(公告)日：2017-04-11

申请号：US14960041

申请日：2015-12-04

Applicant: United Microelectronics Corp.

Inventor： Hai-Biao Yao ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin ,  Zhi-Biao Zhou

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/033 ,  H01L29/51

CPC classification number: H01L29/7869 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02565 ,  H01L21/0332 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/66969 ,  H01L29/785 ,  H01L29/78606 ,  H01L29/78696

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes an oxide semiconductor protrusion, a source, a drain, an oxide semiconductor layer, a first O-barrier layer, a gate electrode, a second O-barrier layer, and an H-barrier layer. The oxide semiconductor protrusion is disposed on an oxide substrate. The source and the drain are respectively disposed on opposite ends of the oxide semiconductor protrusion. The oxide semiconductor layer is disposed on the oxide substrate and covers the oxide semiconductor protrusion, the source, and the drain. The first O-barrier layer is disposed on the oxide semiconductor layer. The gate electrode is disposed on the first O-barrier layer and across the oxide semiconductor protrusion. The second O-barrier layer is disposed on the gate electrode. The H-barrier layer is disposed on the oxide substrate and covers the second O-barrier layer.

公开(公告)号：US20150357397A1

公开(公告)日：2015-12-10

申请号：US14445416

申请日：2014-07-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Biao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L28/60

Abstract: A semiconductor apparatus including a stacked capacitance structure is provided. The stacked capacitance structure includes a first inner metal layer having a first pad area adjacent to an edge of the first inner metal layer, a first insulating layer disposed on the first inner metal layer and exposing the first pad area, a second inner metal layer disposed on the first insulating layer and having a second pad area adjacent to an edge of the second inner metal layer, a second insulating layer disposed on the second inner metal layer and exposing the second pad area, and a third inner metal layer covering the second inner metal layer and including at least one first slit. The first pad area and the second pad area include a plurality of pads. The first slit corresponds to the second pad area, such that the pads on the second pad area are exposed.

Abstract translation: 提供了包括堆叠电容结构的半导体装置。 堆叠的电容结构包括具有与第一内金属层的边缘相邻的第一焊盘区域的第一内部金属层，设置在第一内部金属层上并暴露第一焊盘区域的第一绝缘层，设置的第二内部金属层 在第一绝缘层上并且具有与第二内金属层的边缘相邻的第二焊盘区域，设置在第二内金属层上并暴露第二焊盘区域的第二绝缘层，以及覆盖第二内金属层的第三内金属层 金属层并且包括至少一个第一狭缝。 第一焊盘区域和第二焊盘区域包括多个焊盘。 第一狭缝对应于第二焊盘区域，使得第二焊盘区域上的焊盘露出。