公开(公告)号：US20150050751A1

公开(公告)日：2015-02-19

申请号：US13965600

申请日：2013-08-13

Applicant: United Microelectronics Corp.

Inventor： Ji Feng ,  Hai-Long Gu ,  Ying-Tu Chen

IPC: H01L21/66

CPC classification number: H01L22/12 ,  H01L21/76205 ,  H01L21/76237 ,  H01L22/20

Abstract: A method of controlling a threshold voltage is provided. The method of controlling a threshold voltage includes performing a film-thickness measuring step to measure the thickness of a film layer on a wafer to obtain a film-thickness value. Then, at least one parameter is decided, selected, or generated according to the film-thickness value. Next, an ion implantation process is performed on the wafer, wherein the ion implantation process is executed according to the parameter to form a threshold voltage adjustment region in the wafer below the film layer.

Abstract translation: 提供了一种控制阈值电压的方法。 控制阈值电压的方法包括进行膜厚测量步骤，以测量晶片上的薄膜层的厚度以获得薄膜厚度值。 然后，根据膜厚度值决定，选择或生成至少一个参数。 接下来，在晶片上进行离子注入工艺，其中根据参数执行离子注入处理，以在薄膜层下方的晶片中形成阈值电压调整区域。

公开(公告)号：US09082660B2

公开(公告)日：2015-07-14

申请号：US13965600

申请日：2013-08-13

Applicant: United Microelectronics Corp.

Inventor： Ji Feng ,  Hai-Long Gu ,  Ying-Tu Chen

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/762

CPC classification number: H01L22/12 ,  H01L21/76205 ,  H01L21/76237 ,  H01L22/20

Abstract: A method of controlling a threshold voltage is provided. The method of controlling a threshold voltage includes performing a film-thickness measuring step to measure the thickness of a film layer on a wafer to obtain a film-thickness value. Then, at least one parameter is decided, selected, or generated according to the film-thickness value. Next, an ion implantation process is performed on the wafer, wherein the ion implantation process is executed according to the parameter to form a threshold voltage adjustment region in the wafer below the film layer.

Abstract translation: 提供了一种控制阈值电压的方法。 控制阈值电压的方法包括进行膜厚测量步骤，以测量晶片上的薄膜层的厚度以获得薄膜厚度值。 然后，根据膜厚度值决定，选择或生成至少一个参数。 接下来，在晶片上进行离子注入工艺，其中根据参数执行离子注入处理，以在薄膜层下方的晶片中形成阈值电压调整区域。

公开(公告)号：US20140357050A1

公开(公告)日：2014-12-04

申请号：US13907996

申请日：2013-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： JI FENG ,  XIAOQING XU ,  Hailong Gu ,  Ying-Tu Chen ,  JINGLING WANG

IPC: H01L21/762 ,  H01L21/768

CPC classification number: H01L21/76229 ,  H01L21/76898

Abstract: A method of forming an isolation structure and a through silicon via includes the following steps. First, at least a first trench and at least a second trench are formed in the substrate by a single etch step. Then, an insulating layer is formed to simultaneously fill up the first trench and cover a sidewall and a bottom of the second trench. After that, a conductive layer is formed to fill in the second trench. Subsequently, the insulating layer and the conductive layer on a front side of the substrate are removed. Later, a back side of the substrate is thinned to expose the conductive layer in the second trench. The insulating layer in the first trench serves as an insulating filling, and the insulating layer on the sidewall of the second trench serves as a liner of the through silicon via.

Abstract translation: 形成隔离结构和通硅通孔的方法包括以下步骤。 首先，通过单个蚀刻步骤在衬底中形成至少第一沟槽和至少第二沟槽。 然后，形成绝缘层以同时填充第一沟槽并覆盖第二沟槽的侧壁和底部。 之后，形成导电层以填充第二沟槽。 随后，去除衬底正面上的绝缘层和导电层。 之后，使基板的背面变薄以露出第二沟槽中的导电层。 第一沟槽中的绝缘层用作绝缘填充物，并且第二沟槽的侧壁上的绝缘层用作穿硅通孔的衬垫。