公开(公告)号：US20240256459A1

公开(公告)日：2024-08-01

申请号：US18160221

申请日：2023-01-26

Applicant: VMware, Inc.

Inventor： Pratap SUBRAHMANYAM ,  Venkata Subhash Reddy PEDDAMALLU ,  Isam Wadih AKKAWI ,  Andreas Georg NOWATZYK ,  Rajesh VENKATASUBRAMANIAN ,  Yijiang YUAN ,  Adarsh Seethanadi NAYAK ,  Nishchay DUA ,  Sreekanth SETTY

IPC: G06F12/0882 ,  G06F12/0891 ,  G06F12/1009

CPC classification number: G06F12/0882 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/1027

Abstract: A memory hierarchy includes a first memory and a second memory that is at a lower position in the memory hierarchy than the first memory. A method of managing the memory hierarchy includes: observing, over a first period of time, accesses to pages of the first memory; in response to determining that no page in a first group of pages was accessed during the first period of time, moving each page in the first group of pages from the first memory to the second memory; and in response to determining that the number of pages in other groups of pages of the first memory, which were accessed during the first period of time, is less than a threshold number of pages, moving each page in the other group of pages, that was not accessed during the first period of time from the first memory to the second memory.

公开(公告)号：US20230069152A1

公开(公告)日：2023-03-02

申请号：US17411792

申请日：2021-08-25

Applicant: VMware, Inc.

Inventor： Isam Wadih AKKAWI ,  Andreas NOWATZYK ,  Pratap SUBRAHMANYAM ,  Nishchay DUA ,  Adarsh Seethanadi NAYAK ,  Venkata Subhash Reddy PEDDAMALLU ,  Irina CALCIU

IPC: G06F12/0804 ,  G06F13/16 ,  G06F13/40

Abstract: In a computer system, a processor and an I/O device controller communicate with each other via a coherence interconnect and according to a cache coherence protocol. Registers of the I/O device controllers are mapped to the cache coherent memory space to allow the processor to treat the registers as cacheable memory. As a result, latency of processor commands executed by the I/O device controller is decreased, and size of data stored in the I/O device controller that can be accessed by the processor is increased from the size of a single register to the size of an entire cache line.

公开(公告)号：US20220414017A1

公开(公告)日：2022-12-29

申请号：US17355941

申请日：2021-06-23

Applicant: VMware, Inc.

Inventor： Nishchay DUA ,  Andreas NOWATZYK ,  Isam Wadih AKKAWI ,  Pratap SUBRAHMANYAM ,  Venkata Subhash Reddy PEDDAMALLU ,  Adarsh Seethanadi NAYAK

IPC: G06F12/0897 ,  G06F12/0831 ,  G06F12/0862 ,  G06F9/455

Abstract: The state of cache lines transferred into an out of caches of processing hardware is tracked by monitoring hardware. The method of tracking includes monitoring the processing hardware for cache coherence events on a coherence interconnect between the processing hardware and monitoring hardware, determining that the state of a cache line has changed, and updating a hierarchical data structure to indicate the change in the state of said cache line. The hierarchical data structure includes a first level data structure including first bits, and a second level data structure including second bits, each of the first bits associated with a group of second bits. The step of updating includes setting one of the first bits and one of the second bits in the group corresponding to the first bit that is being set, according to an address of said cache line.