Memory die layouts for failure protection in SSDs

    公开(公告)号:US10770431B1

    公开(公告)日:2020-09-08

    申请号:US16287948

    申请日:2019-02-27

    Abstract: The present disclosure generally relates to storage devices comprising a memory device having a layout optimized for data failure protection. A storage device comprises a memory device having a first package and a second package disposed adjacent to the first package. The first package comprises an even number of memory die having a first storage capacity, and the second package comprises two memory die having a second storage capacity. A first half of the memory dies of the first package and a first memory die of the second package are coupled to a first channel. A second half of the memory dies of the first package and a second memory die of the second package are coupled to a second channel parallel to the first channel.

    Write latency reduction
    3.
    发明授权

    公开(公告)号:US10528265B1

    公开(公告)日:2020-01-07

    申请号:US15256522

    申请日:2016-09-03

    Abstract: A data storage system includes a plurality of Data Storage Devices (DSDs). A write command is sent to each DSD of the plurality of DSDs to each store one or more erasure coded shards of an overprovisioned number of shards. The overprovisioned number of shards is generated from an erasure coding on data to provide at least a predetermined level of data reliability. Write complete indications are received for a threshold number of shards less than the overprovisioned number of shards, with each write complete indication indicating that one or more shards of the overprovisioned number of shards has been stored in a DSD. It is determined that the data has been written with at least the predetermined level of data reliability after receiving write complete indications for the threshold number of shards, but before receiving write complete indications for all of the overprovisioned number of shards.

    Read tail latency reduction
    4.
    发明授权

    公开(公告)号:US10374634B2

    公开(公告)日:2019-08-06

    申请号:US15373450

    申请日:2016-12-08

    Abstract: An individual latency indicator is determined for each Data Storage Device (DSD) or memory portion of a DSD storing one or more erasure coded shards generated from an erasure coding on initial data. Each individual latency indicator is associated with a latency in retrieving an erasure coded shard stored in a respective DSD or memory portion. At least one collective latency indicator is determined using determined individual latency indicators, with the at least one collective latency indicator being associated with a latency in retrieving multiple erasure coded shards. The at least one collective latency indicator is compared to a latency limit, and a subset of erasure coded shards is selected to retrieve based on the comparison of the at least one collective latency indicator to the latency limit.

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