公开(公告)号：US10896911B2

公开(公告)日：2021-01-19

申请号：US16374351

申请日：2019-04-03

Applicant: Winbond Electronics Corp.

Inventor： Hsu-Chi Cho ,  Cheng-Ta Yang

IPC: H01L27/11521 ,  H01L29/66 ,  H01L21/3115 ,  H01L21/3215 ,  H01L21/3205 ,  H01L29/49 ,  H01L29/40 ,  H01L21/311 ,  H01L21/28 ,  H01L27/11531 ,  H01L27/11558 ,  H01L27/11526 ,  H01L27/115 ,  H01L29/788

Abstract: A method for forming a memory device is provided. The method includes forming a floating gate on a substrate, and forming a control gate on the floating gate. The method also includes forming a mask layer on the control gate, and forming a spacer on a sidewall of the mask layer, wherein a sidewall of the control gate and a sidewall of the floating gate is covered by the spacer. The method further includes performing an ion implantation process to implant a dopant into a top portion of the spacer, and performing a wet etching process to expose the sidewall of the control gate.

公开(公告)号：US10157930B2

公开(公告)日：2018-12-18

申请号：US15353717

申请日：2016-11-16

Applicant: Winbond Electronics Corp.

Inventor： Chun-Hsu Chen ,  Hsu-Chi Cho

IPC: H01L27/115 ,  H01L29/788 ,  H01L21/28 ,  H01L27/11546 ,  H01L27/11524 ,  H01L27/11529

Abstract: A method for fabricating a memory device is provided. In the method, a first gate dielectric layer is formed on a substrate in a first region. A second gate dielectric layer is formed on the substrate in a second region and a third region. A first conductive layer is formed on the substrate. A first dielectric layer is directly formed on the first conductive layer. One portion of the first dielectric layer, one portion of the first conductive layer, and one portion of the second gate dielectric layer in the second region are removed. A third gate dielectric layer and a second conductive layer are formed sequentially on the substrate in the second region. A third conductive layer and a second dielectric layer are formed sequentially on the substrate. Isolation structures are formed in the substrate. Here, the isolation structures penetrate the second dielectric layer and extend into the substrate.

公开(公告)号：US20180061848A1

公开(公告)日：2018-03-01

申请号：US15353717

申请日：2016-11-16

Applicant: Winbond Electronics Corp.

Inventor： Chun-Hsu Chen ,  Hsu-Chi Cho

IPC: H01L27/115 ,  H01L29/788 ,  H01L21/28

CPC classification number: H01L27/11546 ,  H01L21/28273 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/7883

Abstract: A method for fabricating a memory device is provided. In the method, a first gate dielectric layer is formed on a substrate in a first region. A second gate dielectric layer is formed on the substrate in a second region and a third region. A first conductive layer is formed on the substrate. A first dielectric layer is directly formed on the first conductive layer. One portion of the first dielectric layer, one portion of the first conductive layer, and one portion of the second gate dielectric layer in the second region are removed. A third gate dielectric layer and a second conductive layer are formed sequentially on the substrate in the second region. A third conductive layer and a second dielectric layer are formed sequentially on the substrate. Isolation structures are formed in the substrate. Here, the isolation structures penetrate the second dielectric layer and extend into the substrate.