公开(公告)号：US20250036848A1

公开(公告)日：2025-01-30

申请号：US18227225

申请日：2023-07-27

Applicant: XILINX, INC.

Inventor： Aashish TRIPATHI ,  Sundeep Ram Gopal AGARWAL ,  Ashit DEBNATH ,  Atreyee SAHA ,  Praful JAIN

IPC: G06F30/398 ,  G06F30/392

Abstract: A method for predicting voltage drop on a power delivery network of a 3D stacked device includes receiving a spatial power distribution map of a plurality of semiconductor dies of the 3D stacked device, receiving a spatial power source node location map for a plurality of power source nodes coupled to the 3D stacked device, dividing vertically the spatial power distribution map and the spatial power source node location map into overlapping windows, determining a voltage drop map in each of the windows based on the divided spatial power distribution map and the divided spatial power source node location map, and combining the voltage drop map in each of the windows to form a composite voltage drop map.

公开(公告)号：US20240345977A1

公开(公告)日：2024-10-17

申请号：US18134994

申请日：2023-04-14

Applicant: XILINX, INC.

Inventor： Dinesh D. GAITONDE ,  Aashish TRIPATHI ,  Ashit DEBNATH ,  Davis Boyd MOORE ,  Maithilee Rajendra KULKARNI ,  Abhishek Kumar JAIN

IPC: G06F13/40

CPC classification number: G06F13/4059 ,  G06F13/4068

Abstract: A 3D device includes a first semiconductor chip and a second semiconductor chip stacked vertically. The first semiconductor chip includes a first plurality of tiles. The second semiconductor chip includes a second plurality of tiles. A bus electrically couples each of the first plurality of tiles to a corresponding one of the second plurality of tiles based on assignments of the first plurality of tiles and the second plurality of tiles to tile-to-tile pairs that define a minimized sum of bus delays among each possible tile-to-tile pairs. In each tile-to-tile pair, a net electrically couples each of a first plurality of pins to a corresponding one of a second plurality of pins based on assignments of the first plurality of pins to the second plurality of pins that define a minimized sum of net delays among each possible pin-to-pin pairs.