公开(公告)号：US20240429145A1

公开(公告)日：2024-12-26

申请号：US18214381

申请日：2023-06-26

Applicant: XILINX, INC.

Inventor： Praful JAIN ,  Brian C. GAIDE ,  Martin L. VOOGEL

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

Abstract: Embodiments herein describe techniques to build multi-die field-programmable gate arrays (FPGAs) using chip-on-wafer (CoW) technology. In an embodiment, FPGA chiplets (i.e., dies) and an interposer substrate include respective hybrid bonding connectors. Metal layers of the interposer substrate are patterned to provide inter-die communications amongst the multiple dies via the hybrid bonding connectors, and the dies communicate with one another via the hybrid bonding connectors using a non-serialized protocol native to the FPGA. The dies may communicate with one another through edge-based hybrid bonding connectors (e.g., in a symmetrical fashion). The metal layers of the interposer substrate may also support intra-die communications (e.g., data, clocks, and/or controls) and/or provide power, clock(s), and/or configuration parameters to the dies via hybrid bonding connectors within central regions of the dies. The IC device may include more than 1000 tracks per millimeter (e.g., more than 1600, 2800, 3500, or greater).

公开(公告)号：US20250036848A1

公开(公告)日：2025-01-30

申请号：US18227225

申请日：2023-07-27

Applicant: XILINX, INC.

Inventor： Aashish TRIPATHI ,  Sundeep Ram Gopal AGARWAL ,  Ashit DEBNATH ,  Atreyee SAHA ,  Praful JAIN

IPC: G06F30/398 ,  G06F30/392

Abstract: A method for predicting voltage drop on a power delivery network of a 3D stacked device includes receiving a spatial power distribution map of a plurality of semiconductor dies of the 3D stacked device, receiving a spatial power source node location map for a plurality of power source nodes coupled to the 3D stacked device, dividing vertically the spatial power distribution map and the spatial power source node location map into overlapping windows, determining a voltage drop map in each of the windows based on the divided spatial power distribution map and the divided spatial power source node location map, and combining the voltage drop map in each of the windows to form a composite voltage drop map.

公开(公告)号：US20210143127A1

公开(公告)日：2021-05-13

申请号：US16679063

申请日：2019-11-08

Applicant: XILINX, INC.

Inventor： Praful JAIN ,  Steven P. YOUNG ,  Martin L. VOOGEL ,  Brian C. GAIDE

IPC: H01L25/065 ,  H01L25/00

Abstract: An apparatus includes a first die including a first substrate with first TSVs running through it, a first top metal layer and first chimney stack vias (CSVs) connecting the first TSVs with the first top metal layer. The apparatus further includes an uppermost die including an uppermost substrate and an uppermost top metal layer, and uppermost CSVs connecting the uppermost substrate with the uppermost top metal layer. The first and uppermost dies are stacked face to face, the first TSVs and the first CSVs are mutually aligned, and the dies are configured such that current is delivered to the apparatus from the first TSVs up through the first CSVs, the first and uppermost top metal layers, and the uppermost CSVs.