公开(公告)号：US20240194645A1

公开(公告)日：2024-06-13

申请号：US18079631

申请日：2022-12-12

Applicant: XILINX, INC.

Inventor： Jay T. YOUNG ,  Davis Boyd MOORE ,  Sundeep Ram Gopal AGARWAL ,  Brian C. GAIDE

IPC: H01L25/065 ,  G11C5/02 ,  G11C5/06 ,  H01L23/48 ,  H01L27/02 ,  H01L27/06

CPC classification number: H01L25/0657 ,  G11C5/025 ,  G11C5/063 ,  H01L23/481 ,  H01L27/0207 ,  H01L27/0688 ,  H01L2225/06506

Abstract: An integrated circuit (IC) device includes a block of integrated circuitry that includes functional circuitry and configurable interface circuitry. The configurable interface circuitry includes output circuitry that routes a node of the functional circuitry to an output node of the block, and input circuitry that selectively routes the output node of the block or an input node of the block to the functional circuitry. The output circuitry may route a selectable subset of multiple nodes of the functional circuitry to respective output nodes of the block, and the input circuitry may be configured to route the output nodes of the block back to the functional circuitry in the absence of an adjacent block (e.g., to repurpose the output circuitry), or in addition to interfacing with the adjacent block.

公开(公告)号：US20240345977A1

公开(公告)日：2024-10-17

申请号：US18134994

申请日：2023-04-14

Applicant: XILINX, INC.

Inventor： Dinesh D. GAITONDE ,  Aashish TRIPATHI ,  Ashit DEBNATH ,  Davis Boyd MOORE ,  Maithilee Rajendra KULKARNI ,  Abhishek Kumar JAIN

IPC: G06F13/40

CPC classification number: G06F13/4059 ,  G06F13/4068

Abstract: A 3D device includes a first semiconductor chip and a second semiconductor chip stacked vertically. The first semiconductor chip includes a first plurality of tiles. The second semiconductor chip includes a second plurality of tiles. A bus electrically couples each of the first plurality of tiles to a corresponding one of the second plurality of tiles based on assignments of the first plurality of tiles and the second plurality of tiles to tile-to-tile pairs that define a minimized sum of bus delays among each possible tile-to-tile pairs. In each tile-to-tile pair, a net electrically couples each of a first plurality of pins to a corresponding one of a second plurality of pins based on assignments of the first plurality of pins to the second plurality of pins that define a minimized sum of net delays among each possible pin-to-pin pairs.