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公开(公告)号：US20230299802A1
公开(公告)日：2023-09-21
申请号：US17698871
申请日：2022-03-18
Applicant: XILINX, INC.
Inventor： Hari Bilash DUBEY , Lanka Sasi Rama SUBRAHMANYAM
CPC classification number: H04B1/18 , H04B1/1676
Abstract: Receiver circuitry for an input/output device includes first stage circuitry and second stage. The first stage circuitry has a first input to receive an input signal, voltage adjustment circuitry, and differential amplifier circuitry. The first stage circuitry is coupled to the first input and has a transistor pair to receive the input signal, and adjust a voltage value of the input signal to generate an adjusted signal. The differential amplifier circuitry receives the adjusted signal and a reference signal, and generates a first differential signal and a second differential signal. The second stage circuitry receives the first differential signal and the second differential signal, and generates an output signal based on the first differential signal and the second differential signal.
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Patent Agency Ranking
公开(公告)号：US20240411331A1
公开(公告)日：2024-12-12
申请号：US18207497
申请日：2023-06-08
Applicant: XILINX, INC.
Inventor： Hari Bilash DUBEY , Siva Charan NIMMAGADDA
IPC: G05F1/56
Abstract: On chip integrated circuit supply voltage regulator has a reference voltage that varies, based on process and temperature conditions of the integrated circuit. Supply voltage is boosted up if the active transistor load devices operate in a Slow-Slow process condition and/or temperature rises. Higher supply voltage improves the system performance (jitter/delay) if the load network includes switching components. If the active transistor load devices operate in a Fast-Fast process condition then the supply voltage is reduced without loss of performance and a savings in power. The variable reference voltage is generated based on process and temperature conditions of the semiconductor integrated circuit devices (transistors). The voltage regulator will automatically have its variable reference voltage adjusted based upon the process condition fabrication and temperature of the areas of the integrated circuit where the active transistor load devices are located.
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公开(公告)号：US20240201718A1
公开(公告)日：2024-06-20
申请号：US18082921
申请日：2022-12-16
Applicant: XILINX, INC.
IPC: G05F1/56 , H03K17/687
CPC classification number: G05F1/56 , H03K17/6872 , H03K17/6874
Abstract: An input/output (I/O) buffer is implemented without an auxiliary power supply (VCCAUX). The input/output (I/O) buffer includes a connection to a VCCO power supply, a connection to a VCCINT power supply, a connection to a reference voltage, and a VCCO detection circuit coupled to a bias generation circuit. Further, the I/O buffer includes a transmitter circuit coupled to the bias generation circuit, and a receiver circuit coupled to an I/O pad.
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4.发明公开公开(公告)号：US20240283448A1
公开(公告)日：2024-08-22
申请号：US18110772
申请日：2023-02-16
Applicant: XILINX, INC.
IPC: H03K17/687 , H03K3/356
CPC classification number: H03K17/6872 , H03K3/356113 , H03F3/45179
Abstract: The Hot Carrier Injection effect is a phenomenon present in semiconductor devices, where charges are trapped in the gate oxide region and degrade the device. Hot carrier Injection (HCI) is one of the major problems in lower voltage technologies due to lower voltage tolerance limits of MOS devices. Due to this HCI effect, designing high voltage, wide range (i.e., supply voltage ranges: 3.3 v, 2.5 v, and 1.8 v) I/O buffers has become challenging. The HCI effect is common in input/output (I/O) buffers that use bias generation circuits for wide voltage ranges. Disclosed here are methods and systems employed to provide reliable bias generation in an I/O buffer or other semiconductor circuit. This limits the device drain to source voltage (Vds) in the bias circuits and I/O buffer so as to mitigate the hot carrier Injection (HCI) effect.
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公开(公告)号：US20240128974A1
公开(公告)日：2024-04-18
申请号：US17964762
申请日：2022-10-12
Applicant: XILINX, INC.
Inventor： Hari Bilash DUBEY
IPC: H03K17/687
CPC classification number: H03K17/6872
Abstract: Signal routing and EMIR requirements are causing increased demand for metal resources. The cost of metal resources is also an issue. The design and sign-off of on-chip drivers for driving signals from one chip location to another is complicated by requirements for power integrity and signal routing. This disclosure addresses routing resource bottlenecks and power requirements by introducing a low power driver useable in a high speed SERDES scheme. A voltage clipping high speed and low swing driver is disclosed. Threshold switching voltage of the transmitted signal is controlled by a process and temperature compensated biasing scheme. A reference voltage generation circuitry along with a simple receiver demonstrates the capability of this receiver. This transceiver scheme can be used on an on-chip or off-chip SERDES application to send/receive low speed signals serially. Use of this novel technique addresses the metal resource issue along with EMIR and SIPI requirements.
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公开(公告)号：US20230086781A1
公开(公告)日：2023-03-23
申请号：US17482336
申请日：2021-09-22
Applicant: XILINX, INC.
Inventor： Siva Charan NIMMAGADDA , Xiaobao WANG , Vinit SHAH , Sabarathnam EKAMBARAM , Hari Bilash DUBEY
Abstract: Examples describe a duty cycle correction circuit for correcting duty cycle distortion from memory. One example is an integrated circuit for correcting an input clock signal. The integrated circuit includes a first leg circuit and a second leg circuit. The first leg circuit and the second leg circuit both comprise a charging circuit and a discharging circuit. Each charging circuit comprises a first plurality of transistors and each discharging circuit comprises a second plurality of transistors. The charging circuit is coupled to the discharging circuit in series. A number of transistors of the first plurality of transistors in the first leg circuit is different from a number of transistors of the first plurality of transistors in the second leg circuit.
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