公开(公告)号：US20230086781A1

公开(公告)日：2023-03-23

申请号：US17482336

申请日：2021-09-22

Applicant: XILINX, INC.

Inventor： Siva Charan NIMMAGADDA ,  Xiaobao WANG ,  Vinit SHAH ,  Sabarathnam EKAMBARAM ,  Hari Bilash DUBEY

IPC: H03K5/156 ,  G11C7/22 ,  H03K5/135 ,  H03K5/134

Abstract: Examples describe a duty cycle correction circuit for correcting duty cycle distortion from memory. One example is an integrated circuit for correcting an input clock signal. The integrated circuit includes a first leg circuit and a second leg circuit. The first leg circuit and the second leg circuit both comprise a charging circuit and a discharging circuit. Each charging circuit comprises a first plurality of transistors and each discharging circuit comprises a second plurality of transistors. The charging circuit is coupled to the discharging circuit in series. A number of transistors of the first plurality of transistors in the first leg circuit is different from a number of transistors of the first plurality of transistors in the second leg circuit.

公开(公告)号：US20240361948A1

公开(公告)日：2024-10-31

申请号：US18141229

申请日：2023-04-28

Applicant: XILINX, INC.

Inventor： Sabarathnam EKAMBARAM ,  Xiaobao WANG

IPC: G06F3/06 ,  H03K5/13 ,  H03K17/16

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0673 ,  H03K5/13 ,  H03K17/162

Abstract: A memory controller includes driver circuitry, which includes main driver circuitry and hold driver circuitry. The main driver circuitry and hold driver circuitry are connected to an output node. The main driver circuitry comprises driver slice circuitries and outputs a first output signal to the output node based on a first input signal and a second input signal and a number of activated driver slice circuitries. The hold drive circuitry receive the first input signal and outputs a second output signal. The second output signal is delayed with reference to the first output signal by a first delay amount.