公开(公告)号：US11604490B1

公开(公告)日：2023-03-14

申请号：US17500711

申请日：2021-10-13

Applicant: XILINX, INC.

Inventor： Roswald Francis ,  Edward Cullen

IPC: G06F1/10 ,  H03H11/04 ,  H02M3/155 ,  G05F1/46

Abstract: Techniques and apparatus for reducing low frequency power supply spurs in clock signals. One example circuit generally includes a first power supply circuit configured to generate a first power supply voltage on a first power supply rail, a second power supply circuit configured to generate a second power supply voltage on a second power supply rail, a clock distribution network, and a feedback circuit coupled between the second power supply rail and at least one input of the first power supply circuit. The feedback circuit may be configured to sense the second power supply voltage, to process the sensed second power supply voltage, and to output at least one feedback signal to control the first power supply circuit based on the processed second power supply voltage. The clock distribution network may include first and second sets of clock drivers powered by the first and second power supply voltages, respectively.

公开(公告)号：US20210281251A1

公开(公告)日：2021-09-09

申请号：US16812130

申请日：2020-03-06

Applicant: Xilinx, Inc.

Inventor： Roswald Francis ,  Christophe Erdmann

IPC: H03K3/356 ,  H03K3/021

Abstract: A differential signal input buffer is disclosed. The differential signal input buffer may receive a differential signal that includes a first signal and a second signal and may be divided into a first section and a second section and. The first section may buffer and/or amplify the first signal based on a first level-shifted second signal. The second section may buffer and/or amplify the second signal based on a first level-shifted first signal. In some implementations, the first section may buffer and/or amplify the first signal based on a second level-shifted second signal. Further, in some implementations, the second section may buffer and/or amplify the second signal based on a second level-shifted first signal.

公开(公告)号：US11183992B1

公开(公告)日：2021-11-23

申请号：US16852729

申请日：2020-04-20

Applicant: Xilinx, Inc.

Inventor： Roswald Francis ,  Bruno Miguel Vaz

IPC: H03K5/02 ,  H03K5/1252

Abstract: A signal buffer is disclosed. The signal buffer may include one or more bias signal generators to bias one or more transistors. The bias signal generators may generate power supply compensated or ground compensated bias signals. The bias signal generators may include a capacitor to provide a high frequency signal path.

公开(公告)号：US11196412B1

公开(公告)日：2021-12-07

申请号：US16732851

申请日：2020-01-02

Applicant: Xilinx, Inc.

Inventor： Roswald Francis ,  Bruno Miguel Vaz

IPC: H03K17/687 ,  H03K17/12 ,  H03M1/12

Abstract: Apparatus and associated methods relate to an input buffer having a source follower connected in series with a push-pull driver to generate a shield reference node that provides conductive traces extending from the shield reference node and disposed between gate traces of the input buffer and a corresponding nearest reference potential node. In an illustrative example, the push-pull driver and the source follower may be capacitively coupled, via the gate traces, to receive an input signal from an input node. In some examples, the shield reference node may also include conductive traces disposed between the input node and/or the gate traces and a corresponding nearest reference potential node such that parts of parasitic capacitances in the input buffer may be shielded. Accordingly, the bandwidth of the input buffer may be advantageously improved. The high frequency return loss (S11) may also be improved accordingly.

公开(公告)号：US11211921B2

公开(公告)日：2021-12-28

申请号：US16812130

申请日：2020-03-06

Applicant: Xilinx, Inc.

Inventor： Roswald Francis ,  Christophe Erdmann

IPC: H03K17/12 ,  H03K3/356 ,  H03K3/021 ,  H03K17/16 ,  H03K19/003 ,  H03K17/687

Abstract: A differential signal input buffer is disclosed. The differential signal input buffer may receive a differential signal that includes a first signal and a second signal and may be divided into a first section and a second section and. The first section may buffer and/or amplify the first signal based on a first level-shifted second signal. The second section may buffer and/or amplify the second signal based on a first level-shifted first signal. In some implementations, the first section may buffer and/or amplify the first signal based on a second level-shifted second signal. Further, in some implementations, the second section may buffer and/or amplify the second signal based on a second level-shifted first signal.

公开(公告)号：US10998864B1

公开(公告)日：2021-05-04

申请号：US16583789

申请日：2019-09-26

Applicant: Xilinx, Inc.

Inventor： Roswald Francis ,  Christophe Erdmann

IPC: H03F1/32 ,  H03F3/45

Abstract: An apparatus for generating an output current including a first distortion current based on a first transconductance and a second distortion current based on a second transconductance is disclosed. The first distortion current may be generated by an amplifier and the second distortion current may be generated by a distortion compensator. The second transconductance may be less than the first transconductance. In some implementations, the second distortion current may reduce the first distortion current output by the apparatus.

公开(公告)号：US10673424B1

公开(公告)日：2020-06-02

申请号：US16388786

申请日：2019-04-18

Applicant: Xilinx, Inc.

Inventor： Roswald Francis ,  Christophe Erdmann

IPC: H03K5/13 ,  H03M1/08 ,  H03K5/00

Abstract: Apparatus and associated methods relating to a switch leakage compensation delay circuit include a compensating transistor configured to passively bypass a leakage current around a capacitor that connects in series with a control transistor. In an illustrative example, the capacitor and the compensating transistor may be connected in parallel between a first node and a second node. The compensating transistor gate may be tied, for example, directly to its source and to the second node. The control transistor may connect its drain to the second node. When a control signal turns off the control transistor, a leakage current of the control transistor may be supplied from a leakage current of the compensating transistor such that the voltage across the capacitor may be maintained substantially constant. The delay circuit may advantageously mitigate the capacitor's voltage droop to reduce clock time skew, for example, in low speed interleaved ADC operation.

公开(公告)号：US12176900B2

公开(公告)日：2024-12-24

申请号：US17884342

申请日：2022-08-09

Applicant: XILINX, INC.

Inventor： Roswald Francis

IPC: H04L25/03 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/0944 ,  H03M1/12

Abstract: An electronic system includes a buffer and analog-to-digital circuitry. The buffer includes buffer circuitry that includes an input node that receives an input signal. The buffer circuitry further includes coil circuitry that is electrically connected to the input node and a first node. The coil circuitry includes a first inductor and a second inductor. Further, the buffer circuitry includes a resistor that is electrically connected to the first node and a second node. A capacitor of the buffer circuitry is electrically connected to the second node and a third node. The third node is disposed between the first inductor and the second inductor. The buffer circuitry is configured to output an output signal based on the input signal.

公开(公告)号：US12040766B2

公开(公告)日：2024-07-16

申请号：US17871699

申请日：2022-07-22

Applicant: XILINX, INC.

Inventor： Roswald Francis

IPC: H03H11/24 ,  H03K19/0175

CPC classification number: H03H11/245 ,  H03K19/017509

Abstract: Attenuation circuitry for a wireless receiver system receives and attenuates an input signal. The attenuation circuitry includes an input pin, coil circuitry, capacitor network circuitry, and inverter circuitry. The input pin receives the input signal. The coil circuitry is electrically connected to the input pin, receives the input signal from the input pin, and outputs an adjusted signal from the input signal. The capacitor network circuitry is electrically connected to the coil circuitry. The capacitor network circuitry receives the adjusted signal from the coil circuitry, and outputs an attenuated signal from the adjusted signal. The inverter circuitry is electrically connected to the capacitor network circuitry. The inverter circuitry receives the attenuated signal and generates an output signal from the attenuated signal. The output signal is output from the attenuation circuitry via an output inductor.

公开(公告)号：US12015419B2

公开(公告)日：2024-06-18

申请号：US17829297

申请日：2022-05-31

Applicant: XILINX, INC.

Inventor： Roswald Francis

IPC: H03M1/10

CPC classification number: H03M1/1033

Abstract: Examples describe a switched capacitor (SC) circuitry calibrated to mitigate the pole-zero (PZ) doublet errors that occur in an analog circuitry. Due to PZ-doublet errors, the slow settling time response of an input step function to an analog circuitry make it impractical to use in applications such as a digital oscilloscope. Mitigating the PZ-doublet errors in the frequency domain is not practical due to the problem of the generation of low frequency sinusoidal tones. The solution disclosed in the present invention is to apply a step function and examine the output's slow settling error waveform. A signal is input to an analog to digital converter, and the output of the converter is processed by a computation that produces calibration codes. Calibration codes are coupled to a SC circuitry to mitigate the PZ-doublet errors. The error waveform is then minimized within a specified accuracy.