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公开(公告)号：US10944414B1
公开(公告)日：2021-03-09
申请号：US16922873
申请日：2020-07-07
Applicant: Xilinx, Inc.
Inventor： Bruno Miguel Vaz , Bob W. Verbruggen , Christophe Erdmann
Abstract: An apparatus and method for sampling an analog signal with analog-to-digital converters (ADCs) is disclosed. The ADCs may be separated into a group of interleaved ADCs and a spare ADC. The interleaved ADCs can sample the analog signal according to an interleaving sequence. An interleaved ADC controller can monitor the inactivity of the spare ADC and can replace one of the interleaved ADCs in the interleaving sequence with the spare ADC based on the inactivity.
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公开(公告)号：US20170346455A1
公开(公告)日：2017-11-30
申请号：US15167197
申请日：2016-05-27
Applicant: Xilinx, Inc.
Inventor： Christophe Erdmann , Diarmuid Collins , Edward Cullen , Ionut C. Cical
CPC classification number: H03F3/45179 , H03F1/301 , H03F1/56 , H03F3/45183 , H03F2200/459 , H03F2203/45288
Abstract: A circuit for receiving an input signal is described. The receiver comprises a first receiver input configured to receive a first input of a differential input signal; a second receiver input configured to receive a second input of a differential input signal; a differential pair having an inverting input and a non-inverting input; a first impedance matching element coupled to the differential pair, wherein the first impedance matching element provides DC impedance matching from the inverting input and non-inverting input of the differential pair; and a second impedance matching element coupled to the differential pair, wherein the second impedance matching element provides AC impedance matching from the inverting input and non-inverting input of the differential pair.
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3.发明授权Current steering with independent biasing between bleed and steering circuitry 有权流量与转向电路之间具有独立偏置的电流转向公开(公告)号：US09000812B1
公开(公告)日：2015-04-07
申请号：US14245540
申请日：2014-04-04
Applicant: Xilinx, Inc.
Inventor： Donnacha Lowney , Christophe Erdmann
CPC classification number: H03K17/162 , H03K19/0013
Abstract: An apparatus relating generally to a current steering cell includes a first bleeder circuit, a second bleeder circuit, a steering circuit, and an output circuit. The first bleeder circuit and the second bleeder circuit are coupled to receive a first current-source bias voltage. The steering circuit is coupled to receive a second current-source bias voltage independent from the first current-source bias voltage.
Abstract translation: 一般涉及当前转向单元的装置包括第一泄放电路，第二泄放电路，转向电路和输出电路。 第一泄放电路和第二泄放电路被耦合以接收第一电流源偏置电压。 转向电路被耦合以接收独立于第一电流源偏置电压的第二电流源偏置电压。
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公开(公告)号：US08890730B2
公开(公告)日：2014-11-18
申请号：US13843909
申请日：2013-03-15
Applicant: Xilinx, Inc.
Inventor： Donnacha Lowney , Christophe Erdmann , Edward Cullen
IPC: H03M1/10
CPC classification number: H03M1/1009 , H03M1/742
Abstract: An apparatus for calibration of a signal converter is disclosed. This apparatus includes a first digital-to-analog converter (“DAC”) and a calibration system coupled to an output port of the first DAC. The calibration system includes a second DAC. The calibration system is configured to provide an adjustment signal responsive to a spurious spectral performance parameter in an output of the first DAC. The spurious spectral performance parameter is sensitive to a timing error associated with the first DAC. The calibration system is coupled to provide the adjustment signal to the first DAC to correct the timing error of the first DAC.
Abstract translation: 公开了一种用于校准信号转换器的装置。 该装置包括第一数模转换器（“DAC”）和耦合到第一DAC的输出端口的校准系统。 校准系统包括第二DAC。 校准系统被配置为响应于第一DAC的输出中的寄生光谱性能参数提供调整信号。 寄生光谱性能参数对与第一个DAC相关的定时误差敏感。 校准系统被耦合以向第一DAC提供调整信号以校正第一DAC的定时误差。
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公开(公告)号：US12191876B2
公开(公告)日：2025-01-07
申请号：US18088982
申请日：2022-12-27
Applicant: Xilinx, Inc.
Inventor： Bob Verbruggen , Christophe Erdmann
IPC: H03M1/10
Abstract: Methods and apparatus for calibrating a gain for a circuit block are disclosed. An example method includes receiving a plurality of quantizer offsets, where the plurality of quantizer offsets represent calibration data for a quantizer configured to quantize an output of the circuit block, determining one or more differences based on one or more first quantizer offsets of the plurality of quantizer offsets and on one or more second quantizer offsets of the plurality of quantizer offsets, and determining an incremental change in a gain associated with the circuit block based on the one or more differences.
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Patent Agency Ranking
公开(公告)号：US11716089B1
公开(公告)日：2023-08-01
申请号：US17696734
申请日：2022-03-16
Applicant: XILINX, INC.
Inventor： Bob W. Verbruggen , Christophe Erdmann
IPC: H03M1/06
CPC classification number: H03M1/0604 , H03M1/0682
Abstract: A biasing scheme for a voltage-to-time converter (VTC). An example biasing circuit generally includes a reference current source; a feedback loop current source; an amplifier having a first input coupled to a target voltage node, having a second input, and having an output coupled to a control input of the reference current source and to a control input of the feedback loop current source; a first capacitive element; a first switch coupled in parallel with the first capacitive element; a second switch coupled between the feedback loop current source and the first capacitive element; and a third switch coupled between the first capacitive element and the second input of the amplifier.
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公开(公告)号：US20210281251A1
公开(公告)日：2021-09-09
申请号：US16812130
申请日：2020-03-06
Applicant: Xilinx, Inc.
Inventor： Roswald Francis , Christophe Erdmann
Abstract: A differential signal input buffer is disclosed. The differential signal input buffer may receive a differential signal that includes a first signal and a second signal and may be divided into a first section and a second section and. The first section may buffer and/or amplify the first signal based on a first level-shifted second signal. The second section may buffer and/or amplify the second signal based on a first level-shifted first signal. In some implementations, the first section may buffer and/or amplify the first signal based on a second level-shifted second signal. Further, in some implementations, the second section may buffer and/or amplify the second signal based on a second level-shifted first signal.
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公开(公告)号：US10886906B1
公开(公告)日：2021-01-05
申请号：US15989623
申请日：2018-05-25
Applicant: Xilinx, Inc.
Inventor： Bob W. Verbruggen , Christophe Erdmann , Conrado K. Mesadri
Abstract: A duty-cycle adjustment circuit receives a differential pair of input signals and generates an output signal based on the differential pair. The duty-cycle adjustment circuit drives the output signal to a logic-high state based on transitions of a first polarity in a first input signal of the differential pair, and drives the output signal to a logic-low state based on transitions of the first polarity in a second input signal of the differential pair. For example, rising-edge transitions of the output signal may be aligned with rising-edge transitions of the first input signal, and falling-edge transitions of the output signal may be aligned with rising-edge transitions of the second input signal. Alternatively, rising-edge transitions of the output signal may be aligned with falling-edge transitions of the first input signal, and falling-edge transitions of the output signal may be aligned with falling-edge transitions of the second input signal.
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公开(公告)号：US10320401B2
公开(公告)日：2019-06-11
申请号：US15784022
申请日：2017-10-13
Applicant: Xilinx, Inc.
Inventor： Augusto R. Ximenes , Bob W. Verbruggen , Christophe Erdmann
Abstract: An example digital-to-time converter (DTC) includes: a delay chain circuit having a plurality of delay cells coupled in sequence, the delay chain circuit including a first input to receive a first clock signal and a second input to receive a second clock signal; and a DEM controller coupled to the delay chain circuit to provide a plurality of control signals to the plurality of delay cells, respectively.
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公开(公告)号：US11664964B2
公开(公告)日：2023-05-30
申请号：US17488112
申请日：2021-09-28
Applicant: XILINX, INC.
Inventor： Hongzhi Zhao , Christophe Erdmann
CPC classification number: H04L5/1461 , H04B1/0057 , H04B1/0067 , H04L27/2607
Abstract: Embodiments herein describe adapting a PIM model to compensate for changing PIM interference. A PIM model can include circuitry that generates a PIM compensation value that compensates for (i.e., mitigates or subtracts) PIM interference caused by transmitting two or more transmitter (TX) carriers in the same path. The disclosed adaptive scheme generates updated coefficients for the PIM model which are calculated after the RX signal has been removed from the RX channel. In this manner, as the PIM interference changes due to environmental conditions (e.g., temperature at the base station), the adaptive scheme can update the PIM model to generate a PIM compensation value that cancels the PIM interference.
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