公开(公告)号：US20210134760A1

公开(公告)日：2021-05-06

申请号：US16672077

申请日：2019-11-01

Applicant: XILINX, INC.

Inventor： Brian C. GAIDE ,  Steven P. YOUNG

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L21/78

Abstract: Examples described herein generally related to multi-chip devices having vertically stacked chips. In an example, a multi-chip device includes a chip stack. The chip stack includes a base chip and a plurality of interchangeable chips. The base chip is directly bonded to a first one of the plurality of interchangeable chips. Each neighboring pair of the plurality of interchangeable chips is directly bonded together in an orientation with a front side of one chip of the respective neighboring pair directly bonded to a backside of the other chip of the respective neighboring pair. Each of the interchangeable chips has a same processing integrated circuit and a same hardware layout. The chip stack can include a distal chip, which can be directly bonded to a second one of the plurality of interchangeable chips.

公开(公告)号：US20220368330A1

公开(公告)日：2022-11-17

申请号：US17876456

申请日：2022-07-28

Applicant: XILINX, INC.

Inventor： Steven P. YOUNG ,  Brian C. GAIDE

IPC: H03K19/17748 ,  G06F1/10 ,  G06F8/40 ,  H03K19/17736

Abstract: An example integrated circuit includes an array of circuit tiles; interconnect coupling the circuit tiles in the array, the interconnect including interconnect tiles each having a plurality of connections that include at least a connection to a respective one of the circuit tiles and a connection to at least one other interconnect tile; and a plurality of local crossbars in each of the interconnect tiles, the plurality of local crossbars coupled to form a non-blocking crossbar, each of the plurality of local crossbars including handshaking circuitry for asynchronous communication.

公开(公告)号：US20200303311A1

公开(公告)日：2020-09-24

申请号：US16571788

申请日：2019-09-16

Applicant: XILINX, INC.

Inventor： Steven P. YOUNG ,  Brian C. GAIDE

IPC: H01L23/538 ,  H01L25/065 ,  H01L21/66

Abstract: Some examples described herein relate to redundancy in a multi-chip stacked device. An example described herein is a multi-chip device. The multi-chip device includes a chip stack including vertically stacked chips. Neighboring pairs of the chips are directly connected together. Each of two or more of the chips includes a processing integrated circuit. The chip stack is configurable to operate a subset of functionality of the processing integrated circuits of the two or more of the chips when any portion of the processing integrated circuits is defective.

公开(公告)号：US20210336622A1

公开(公告)日：2021-10-28

申请号：US16857090

申请日：2020-04-23

Applicant: XILINX, INC.

Inventor： Steven P. YOUNG ,  Brian C. GAIDE

IPC: H03K19/17748 ,  G06F1/10 ,  G06F8/40 ,  H03K19/17736

Abstract: An example integrated circuit includes an array of circuit tiles; interconnect coupling the circuit tiles in the array, the interconnect including interconnect tiles each having a plurality of connections that include at least a connection to a respective one of the circuit tiles and a connection to at least one other interconnect tile; and a plurality of local crossbars in each of the interconnect tiles, the plurality of local crossbars coupled to form a non-blocking crossbar, each of the plurality of local crossbars including handshaking circuitry for asynchronous communication.

公开(公告)号：US20210143127A1

公开(公告)日：2021-05-13

申请号：US16679063

申请日：2019-11-08

Applicant: XILINX, INC.

Inventor： Praful JAIN ,  Steven P. YOUNG ,  Martin L. VOOGEL ,  Brian C. GAIDE

IPC: H01L25/065 ,  H01L25/00

Abstract: An apparatus includes a first die including a first substrate with first TSVs running through it, a first top metal layer and first chimney stack vias (CSVs) connecting the first TSVs with the first top metal layer. The apparatus further includes an uppermost die including an uppermost substrate and an uppermost top metal layer, and uppermost CSVs connecting the uppermost substrate with the uppermost top metal layer. The first and uppermost dies are stacked face to face, the first TSVs and the first CSVs are mutually aligned, and the dies are configured such that current is delivered to the apparatus from the first TSVs up through the first CSVs, the first and uppermost top metal layers, and the uppermost CSVs.