公开(公告)号：US20250005248A1

公开(公告)日：2025-01-02

申请号：US18217339

申请日：2023-06-30

Applicant: XILINX, INC.

Inventor： Martin L. VOOGEL

IPC: G06F30/392

Abstract: Embodiments herein describe devices that include an interposer with a stitch formed from overlapping exposure areas, which may result in the interposer having a total surface area that is greater than a maximum reticle field corresponding to the exposure areas. Two or more integrated circuits (e.g., chiplets) can be disposed on the interposer. At least one of the integrated circuits is disposed over the stitch. The interposer can provide chip-to-chip connections between the integrated circuits.

公开(公告)号：US20240330557A1

公开(公告)日：2024-10-03

申请号：US18128368

申请日：2023-03-30

Applicant: XILINX, INC.

Inventor： Martin L. VOOGEL ,  Matthew H. KLEIN

IPC: G06F30/392 ,  G06F30/398

CPC classification number: G06F30/392 ,  G06F30/398

Abstract: Embodiments herein describe various 2×2 configuration of integrated circuits (ICs), where the ICs can communicate with multiple neighboring ICs using chip-to-chip interfaces. As such, 2×2 configurations are improvements over other horizontal chip integration formats (such as 1×2, 1×3, and 1×4) where some of the ICs can directly communicate with only one other IC.

公开(公告)号：US20230055458A1

公开(公告)日：2023-02-23

申请号：US17405073

申请日：2021-08-18

Applicant: XILINX, INC.

Inventor： Pierre MAILLARD ,  Betty LAU ,  Yanran CHEN ,  Jun LIU ,  Martin L. VOOGEL

IPC: H03K19/003 ,  H03K3/0233 ,  H03K19/20 ,  G06F30/392

Abstract: One example of the present disclosure is an integrated circuit (IC). The IC includes an inverter with an input and an output, a clock transmission gate coupled to the output of the inverter; and a plurality of storage cells. The clock transmission gate is coupled to each of the plurality of storage cells, wherein each of the plurality of storage cells comprises a plurality of nodes arranged based on a minimum spacing.

公开(公告)号：US20210143127A1

公开(公告)日：2021-05-13

申请号：US16679063

申请日：2019-11-08

Applicant: XILINX, INC.

Inventor： Praful JAIN ,  Steven P. YOUNG ,  Martin L. VOOGEL ,  Brian C. GAIDE

IPC: H01L25/065 ,  H01L25/00

Abstract: An apparatus includes a first die including a first substrate with first TSVs running through it, a first top metal layer and first chimney stack vias (CSVs) connecting the first TSVs with the first top metal layer. The apparatus further includes an uppermost die including an uppermost substrate and an uppermost top metal layer, and uppermost CSVs connecting the uppermost substrate with the uppermost top metal layer. The first and uppermost dies are stacked face to face, the first TSVs and the first CSVs are mutually aligned, and the dies are configured such that current is delivered to the apparatus from the first TSVs up through the first CSVs, the first and uppermost top metal layers, and the uppermost CSVs.

公开(公告)号：US20250006694A1

公开(公告)日：2025-01-02

申请号：US18215685

申请日：2023-06-28

Applicant: XILINX, INC.

Inventor： Martin L. VOOGEL ,  Matthew H. KLEIN

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498

Abstract: Examples herein describe techniques for producing a three-dimensional (3D) die stack. The techniques include stacking a first die on top of a second die. The first die is offset from the second die in at least one of an x-direction and a y-direction, and a first routing sub-region of the first die aligns with a second routing sub-region of the second die. The techniques further include stacking a third die on top of the second die. The third die is offset from the second die in at least one of the x-direction and the y-direction, and a third routing sub-region of the third die aligns with a fourth routing sub-region of the second die.

公开(公告)号：US20240429145A1

公开(公告)日：2024-12-26

申请号：US18214381

申请日：2023-06-26

Applicant: XILINX, INC.

Inventor： Praful JAIN ,  Brian C. GAIDE ,  Martin L. VOOGEL

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

Abstract: Embodiments herein describe techniques to build multi-die field-programmable gate arrays (FPGAs) using chip-on-wafer (CoW) technology. In an embodiment, FPGA chiplets (i.e., dies) and an interposer substrate include respective hybrid bonding connectors. Metal layers of the interposer substrate are patterned to provide inter-die communications amongst the multiple dies via the hybrid bonding connectors, and the dies communicate with one another via the hybrid bonding connectors using a non-serialized protocol native to the FPGA. The dies may communicate with one another through edge-based hybrid bonding connectors (e.g., in a symmetrical fashion). The metal layers of the interposer substrate may also support intra-die communications (e.g., data, clocks, and/or controls) and/or provide power, clock(s), and/or configuration parameters to the dies via hybrid bonding connectors within central regions of the dies. The IC device may include more than 1000 tracks per millimeter (e.g., more than 1600, 2800, 3500, or greater).

公开(公告)号：US20240346220A1

公开(公告)日：2024-10-17

申请号：US18134497

申请日：2023-04-13

Applicant: XILINX, INC.

Inventor： Martin L. VOOGEL

IPC: G06F30/347

CPC classification number: G06F30/347

Abstract: Embodiments herein describe arranging TX and RX circuitry in ICs such that rotated and mirrored ICs are aligned when connected in a multiple-chip device. In one embodiment, the TX circuitry (e.g., TX physical layer or PHY) is arranged in one row while the RX circuitry (e.g., RX physical layer or PHY) is arranged in another row. As such, when an IC is rotated or mirrored, at least one TX PHY is aligned with a RX PHY on the other IC. As such, non-crossing chip-to-chip connections can be formed through the interposer.